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NB4N11SMNG

P1-P3P4-P6P7-P9P10-P10
NB4N11S
http://onsemi.com
4
Table 4. DC CHARACTERISTICS, CLOCK INPUTS, LVDS OUTPUTS V
CC
= 3.0 V to 3.6 V, GND = 0 V, T
A
= −40°C to +85°C
Symbol Characteristic Min Typ Max Unit
I
CC
Power Supply Current (Note 8) 35 50 mA
DIFFERENTIAL INPUTS DRIVEN SINGLE−ENDED (Figures 11, 12, 16, and 18)
V
th
Input Threshold Reference Voltage Range (Note 7) GND +100 V
CC
− 100 mV
V
IH
Single−ended Input HIGH Voltage V
th
+ 100 V
CC
mV
V
IL
Single−ended Input LOW Voltage GND V
th
− 100 mV
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Figures 7, 8, 9, 10, 17, and 19)
V
IHD
Differential Input HIGH Voltage 100 V
CC
mV
V
ILD
Differential Input LOW Voltage GND V
CC
− 100 mV
V
CMR
Input Common Mode Range (Differential Configuration) GND + 50 V
CC
− 50 mV
V
ID
Differential Input Voltage (V
IHD
− V
ILD
) 100 V
CC
mV
R
TIN
Internal Input Termination Resistor 40 50 60
W
LVDS OUTPUTS (Note 4)
V
OD
Differential Output Voltage 250 450 mV
DV
OD
Change in Magnitude of V
OD
for Complimentary Output States (Note 9) 0 1 25 mV
V
OS
Offset Voltage (Figure 15) 1125 1375 mV
DV
OS
Change in Magnitude of V
OS
for Complimentary Output States (Note 9) 0 1 25 mV
V
OH
Output HIGH Voltage (Note 5) 1425 1600 mV
V
OL
Output LOW Voltage (Note 6) 900 1075 mV
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
4. LVDS outputs require 100 W receiver termination resistor between differential pair. See Figure 14.
5. V
OH
max = V
OS
max + ½ V
OD
max.
6. V
OL
max = V
OS
min − ½ V
OD
max.
7. V
th
is applied to the complementary input when operating in single−ended mode.
8. Input termination pins open, D/D at the DC level within V
CMR
and output pins loaded with R
L
= 100 W across differential.
9. Parameter guaranteed by design verification not tested in production.
NB4N11S
http://onsemi.com
5
Table 5. AC CHARACTERISTICS V
CC
= 3.0 V to 3.6 V, GND = 0 V; (Note 10)
Symbo
l
Characteristic
−40°C 25°C 85°C
Uni
t
Min Typ Max Min Typ Max Min Typ Max
V
OUTPP
Output Voltage Amplitude (@ V
INPPmin
)f
in
≤ 1.0 GHz
(Figure 4) f
in
= 1.5 GHz
f
in
= 2.0 GHz
220
200
170
350
300
270
250
200
170
350
300
270
250
200
170
350
300
270
mV
f
DATA
Maximum Operating Data Rate 1.5 2.5 1.5 2.5 1.5 2.5 Gb/s
t
PLH
,
t
PHL
Differential Input to Differential Output
Propagation Delay
270 370 470 270 370 470 270 370 470 ps
t
SKEW
Duty Cycle Skew (Note 11)
Within Device Skew (Note 16)
Device−to−Device Skew (Note 15)
8
5
30
45
25
100
8
5
30
45
25
100
8
5
30
45
25
100
ps
t
JITTER
RMS Random Clock Jitter (Note 13) f
in
= 1.0 GHz
f
in
= 1.5 GHz
Deterministic Jitter (Note 14) f
DATA
= 622 Mb/s
f
DATA
= 1.5 Gb/s
f
DATA
= 2.488 Gb/s
0.5
0.5
6
7
10
1
1
20
20
0.5
0.5
6
7
10
1
1
20
20
0.5
0.5
6
7
10
1
1
20
20
ps
V
INPP
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 12)
100 V
CC
−
GND
100 V
CC
−
GND
100 V
CC
−
GND
mV
t
r
t
f
Output Rise/Fall Times @ 250 MHz Q, Q
(20% − 80%)
70 120 170 70 120 170 70 120 170 ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
10.Measured by forcing V
INPPmin
with 50% duty cycle clock source and V
CC
− 1400 mV offset. All loading with an external R
L
= 100 W across
“D” and “D” of the receiver. Input edge rates 150 ps (20%−80%).
11. See Figure 13 differential measurement of t
skew
= |t
PLH
− t
PHL
| for a nominal 50% differential clock input waveform @ 250 MHz.
12.Input voltage swing is a single−ended measurement operating in differential mode.
13.RMS jitter with 50% Duty Cycle clock signal at 750 MHz.
14.Deterministic jitter with input NRZ data at PRBS 2
23
−1 and K28.5.
15.Skew is measured between outputs under identical transition @ 250 MHz.
16.The worst case condition between Q0/Q0 and Q1/Q1 from either D0/D0 or D1/D1, when both outputs have the same transition.
INPUT CLOCK FREQUENCY (GHz)
Figure 4. Output Voltage Amplitude (V
OUTPP
) versus
Input Clock Frequency (f
in
) and Temperature (@ V
CC
= 3.3 V)
OUTPUT VOLTAGE AMPLITUDE (mV)
0
50
100
150
200
250
300
350
400
0.5 1 1.5 2 2.5 30
85°C
−40°C
25°C
NB4N11S
http://onsemi.com
6
TIME (58 ps/div)
Figure 5. Typical Output Waveform at 2.488 Gb/s with PRBS 2
23−1
and OC48 mask
(V
INPP
= 100 mV; Input Signal DDJ = 14 ps)
VOLTAGE (63.23 mV/div)
Device DDJ = 10 ps
R
C
R
C
1.25 kW1.25 kW
1.25 kW1.25 kW
50 W
50 W
Dx
V
TDx
V
TDx
D
x
Figure 6. Input Structure
I
P1-P3P4-P6P7-P9P10-P10

NB4N11SMNG

Mfr. #:
Buy NB4N11SMNG
Manufacturer:
ON Semiconductor
Description:
Clock Buffer LVDS FANOUT BUFF/ TRANS
Lifecycle:
New from this manufacturer.
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