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GTL2005PW/DG,118

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19
1. General description
The GTL2005 is a quad translating transceiver designed for 3.3 V system interface with a
GTL/GTL+ bus.
The direction pin (DIR) allows the part to function as either a GTL-to-TTL sampling
receiver or as a TTL-to-GTL interface.
The GTL2005 LVTTL interface is tolerant up to 5.5 V allowing direct access to TTL or 5 V
CMOS outputs.
The GTL2005 V
ref
linearity degrades below 0.8 V (see Section 10.1). If the application
allows, use the GTL2014, otherwise more closely review noise margins.
2. Features
n Operates as a quad GTL/GTL+ sampling receiver or as a LVTTL/TTL to GTL/GTL+
driver
n Quad bidirectional bus interface
n 3.0 V to 3.6 V operation with 5 V tolerant LVTTL I/O
n Live insertion/extraction permitted
n Latch-up protection exceeds 500 mA per JESD78
n ESD protection exceeds 2000 V HBM per JESD22-A114, 150 V MM per
JESD22-A115, and 1000 V CDM per JESD22-CC101
n Package offered: TSSOP14
GTL2005
Quad GTL/GTL+ to LVTTL/TTL bidirectional non-latched
translator
Rev. 07 — 3 February 2009 Product data sheet
Fig 1. GTL2005/GTL2014 positioning
002aab378
GTL−
GTL
GTL+
fast t
PD
slow t
PD
GTL2014
GTL2005
GTL2005_7 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 07 — 3 February 2009 2 of 19
NXP Semiconductors
GTL2005
Quad GTL/GTL+ to LVTTL/TTL bidirectional non-latched translator
3. Quick reference data
[1] All typical values are measured at V
CC
= 3.3 V and T
amb
=25°C.
4. Ordering information
Table 1. Quick reference data
V
CC
= 3.3 V
±
0.3 V
Symbol Parameter Conditions Min Typ
[1]
Max Unit
C
i
input capacitance control inputs;
V
I
=3.0Vor0V
- 2.3 3.5 pF
C
io
input/output capacitance A port;
V
O
=V
TT
or0V
- 3.4 5.0 pF
B port;
V
O
= 3.0 V or 0 V
- 6.0 7.0 pF
GTL; V
ref
= 0.8 V
t
PLH
propagation delay, Bn to An see Figure 7 - 2.1 2.3 ns
t
PHL
- 1.9 2.6 ns
t
PLH
propagation delay, An to Bn see Figure 8 - 4.1 5.9 ns
t
PHL
- 4.4 5.9 ns
Table 2. Ordering information
T
amb
=
−
40
°
C to +85
°
C
Type number Topside
mark
Package
Name Description Version
GTL2005PW GTL2005 TSSOP14 plastic thin shrink small outline package;
14 leads; body width 4.4 mm
SOT402-1
GTL2005_7 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 07 — 3 February 2009 3 of 19
NXP Semiconductors
GTL2005
Quad GTL/GTL+ to LVTTL/TTL bidirectional non-latched translator
5. Functional diagram
6. Pinning information
6.1 Pinning
Fig 2. Logic diagram of GTL2005
002aab151
GTL2005
B0
B1
B2
B3
A0
A1
A2
A3
VREF DIR
Fig 3. Pin configuration for TSSOP14
GTL2005PW
DIR V
CC
A0 B0
A1 B1
VREF GND
A2 B2
A3 B3
GND GND
002aab150
1
2
3
4
5
6
7
8
10
9
12
11
14
13
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19

GTL2005PW/DG,118

Mfr. #:
Buy GTL2005PW/DG,118
Manufacturer:
NXP Semiconductors
Description:
Translation - Voltage Levels 4-BIT BI-DIREC
Lifecycle:
New from this manufacturer.
Delivery:
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