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CY621472E30LL-45ZSXI
P1-P3
P4-P6
P7-P9
P10-P12
P13-P15
P16-P16
CY621472E30 MoBL
®
Document Number: 001-67798 Rev
. *F
Page 10 of 16
Figure 8. Write Cycl
e No. 3 (WE
Controlled, OE
LO
W)
[29, 30, 31]
Figure 9. Write Cycle No. 4 (BHE
/BLE
Controlled, OE
LOW)
[29, 30]
Switching W
aveforms
(continued)
DATA
IN
t
HD
t
SD
t
LZWE
t
PWE
t
SA
t
HA
t
AW
t
SCE
t
WC
t
HZWE
t
BW
NOTE 32
CE
ADDRESS
WE
DATA I/O
BHE
/BLE
t
HD
t
SD
t
SA
t
HA
t
AW
t
WC
DATA
IN
t
BW
t
SCE
t
PWE
t
HZWE
t
LZWE
NOTE 32
DATA I/O
ADDRESS
CE
WE
BHE
/BLE
Notes
29.
CE
refers to the internal logical combination of CE
1
and CE
2
such that when CE
1
is LOW and CE
2
is HIGH, CE
is LOW. For all other
cases CE
is HIGH.
30.
If CE
goes HIGH simul
taneously with WE
= V
IH
, the output remains in a high impedance st
ate.
31.
The minimum write cycle pulse width should be equal to the sum of t
HZWE
and t
SD.
32.
During this period, the I/Os are in output state. Do not apply input si
gnals.
CY621472E30 MoBL
®
Document Number: 001-67798 Rev
. *F
Page 1
1 of 16
T
ruth T
able
CE
1
CE
2
WE
OE
BHE
BLE
I/Os
Mode
Power
HX
[33]
X
X
X
X
High Z
Deselect/Power-down
S
tandby (I
SB
)
X
[33]
L
X
X
X
X
High Z
Desele
ct/Power-down
S
tandby (I
SB
)
X
[33]
X
[33]
X
X
H
H
High Z
Deselect/Power-d
own
S
tandby (I
SB
)
L
H
H
L
L
L
Data out (I/O
0
–I/O
15
)
Read
Active (I
CC
)
L
H
H
L
H
L
Dat
a out (I/O
0
–I/O
7
);
I/O
8
–I/O
15
in High Z
Read
Active (I
CC
)
L
H
H
L
L
H
Data
out (I/O
8
–I/O
15
);
I/O
0
–I/O
7
in High Z
Read
Active (I
CC
)
L
H
H
H
L
L
High Z
Output disabled
Active (I
CC
)
L
H
H
H
H
L
High Z
Output disabled
Active (I
CC
)
L
H
H
H
L
H
High Z
Output disabled
Active (I
CC
)
L
H
L
X
L
L
Dat
a in (I/O
0
–I/O
15
)
Write
Active (I
CC
)
L
H
L
X
H
L
Data in (I/O
0
–I/O
7
);
I/O
8
–I/O
15
in High Z
Write
Active (I
CC
)
LHLX
LH
D
a
t
a
i
n
(
I
/
O
8
–I/O
15
);
I/O
0
–I/O
7
in High Z
Write
Active (I
CC
)
Note
33.
The ‘X’ (Don’t care) state for the chip enables (CE
1
and CE
2
) in the truth table
refer to the logic state (either HIGH or LOW). Inter
mediate voltage levels on these
pins is not permit
ted.
CY621472E30 MoBL
®
Document Number: 001-67798 Rev
. *F
Page 12 of 16
Ordering Code Definitions
Ordering Information
Spee
d
(ns)
Ordering Code
Package
Diagram
Package T
ype
Operating
Range
45
CY621472
E30LL-45ZSXI
51-85087
44-pin TSOP II (Pb-free)
Industrial
T
emperature Range: I = Industrial
Pb-free
Package T
ype: ZS = 44-pin TSOP II
S
peed
Grade: 45 = 45
ns
Low Power
V
oltage Range: 30
= 3 V T
y
pical
Process T
echnology: E = 90 nm
Dual Chip Enable
Bus Width: 7 = × 16
Density: 4 = 4-Mbit
Family Code: 621 = MoBL SR
AM family
Company ID: CY = Cypress
CY
45
ZS
621
4
7
E
30
LL
X
2
-
I
P1-P3
P4-P6
P7-P9
P10-P12
P13-P15
P16-P16
CY621472E30LL-45ZSXI
Mfr. #:
Buy CY621472E30LL-45ZSXI
Manufacturer:
Cypress Semiconductor
Description:
SRAM 4Mb 3V 45ns 256K x 16 LP SRAM
Lifecycle:
New from this manufacturer.
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