CY621472E30 MoBL
®
Document Number: 001-67798 Rev. *F Page 4 of 16
Maximum Ratings
Exceeding the maximum ratings may impair the useful life of the
device. User guidelines are not tested.
Storage temperature ................................ –65 °C to +150 °C
Ambient temperature with
power applied .......................................... –55 °C to +125 °C
Supply voltage to ground
potential ...........................–0.3 V to +3.9 V (V
CCmax
+ 0.3 V)
DC Voltage Applied to Outputs
in High Z State
[2, 3]
............ –0.3 V to 3.9 V (V
CCmax
+ 0.3 V)
DC input voltage
[2, 3]
......... –0.3 V to 3.9 V (V
CCmax
+ 0.3 V)
Output current into outputs (LOW) ............................. 20 mA
Static discharge voltage
(MIL-STD-883, Method 3015) ................................ > 2001 V
Latch up current...................................................... > 200 mA
Operating Range
Device Range
Ambient
Temperature
V
CC
[4]
CY621472E30LL Industrial –40 °C to +85 °C 2.2 V to 3.6 V
Electrical Characteristics
Over the Operating Range
Parameter Description Test Conditions
45 ns
Unit
Min Typ
[5]
Max
V
OH
Output HIGH voltage I
OH
= –0.1 mA 2.0 V
I
OH
= –1.0 mA, V
CC
> 2.70 V 2.4 V
V
OL
Output LOW voltage I
OL
= 0.1 mA 0.4 V
I
OL
= 2.1 mA, V
CC
= 2.70 V 0.4 V
V
IH
Input HIGH voltage V
CC
= 2.2 V to 2.7 V 1.8 V
CC
+ 0.3 V
V
CC
= 2.7 V to 3.6 V 2.2 V
CC
+ 0.3 V
V
IL
Input LOW voltage V
CC
= 2.2 V to 2.7 V –0.3 0.6 V
V
CC
= 2.7 V to 3.6 V –0.3 0.8 V
I
IX
Input leakage current GND < V
I
< V
CC
–1 +1 A
I
OZ
Output leakage current GND < V
O
< V
CC
, Output Disabled –1 +1 A
I
CC
V
CC
operating supply current f = f
max
= 1/t
RC
V
CC
= V
CC(max)
I
OUT
= 0 mA
CMOS levels
–1520mA
f = 1 MHz 2 2.5
I
SB1
[6]
Automatic CE power-down
current – CMOS inputs
CE
1
> V
CC
– 0.2 V, CE
2
0.2 V,
V
IN
> V
CC
– 0.2 V, V
IN
< 0.2 V,
f = f
max
(address and data only),
f = 0 (OE, BHE, BLE and WE),
V
CC
= 3.60 V
–17A
I
SB2
[6]
Automatic CE Power down
current – CMOS inputs
CE
1
> V
CC
– 0.2 V or CE
2
< 0.2 V or
(BHE and BLE) > V
CC
– 0.2 V,
V
IN
> V
CC
– 0.2 V or V
IN
< 0.2 V,
f = 0, V
CC
= 3.60 V
–17A
Notes
2. V
IL(min)
= –2.0 V for pulse durations less than 20 ns.
3. V
IH(max)
= V
CC
+ 0.75 V for pulse durations less than 20 ns.
4. Full device AC operation assumes a minimum of 100 s ramp time from 0 to V
CC(min)
and 200 s wait time after V
CC
stabilization.
5. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
CC
= V
CC(typ)
, T
A
= 25 °C.
6. Chip enables (CE
1
and CE
2
) need to be tied to CMOS levels to meet the I
SB1
/ I
SB2
/ I
CCDR
spec. Other inputs can be left floating.
CY621472E30 MoBL
®
Document Number: 001-67798 Rev. *F Page 5 of 16
Capacitance
Parameter
[7]
Description Test Conditions Max Unit
C
IN
Input capacitance T
A
= 25 °C, f = 1 MHz, V
CC
= V
CC(typ)
10 pF
C
OUT
Output capacitance 10 pF
Thermal Resistance
Parameter
[7]
Description Test Conditions
44-pin TSOP II
Package
Unit
JA
Thermal resistance
(junction to ambient)
Still Air, soldered on a 3 × 4.5 inch, two-layer printed circuit
board
77 C/W
JC
Thermal resistance
(junction to case)
13 C/W
AC Test Loads and Waveforms
Figure 2. AC Test Loads and Waveforms
V
CC
V
CC
OUTPUT
R2
30 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
Rise Time = 1 V/ns
Fall Time = 1 V/ns
OUTPUT V
ALL INPUT PULSES
R
TH
R1
Equivalent to: THEVENIN EQUIVALENT
Parameters 2.50 V 3.0 V Unit
R1 16667 1103
R2 15385 1554
R
TH
8000 645
V
TH
1.20 1.75 V
Note
7. Tested initially and after any design or process changes that may affect these parameters.
CY621472E30 MoBL
®
Document Number: 001-67798 Rev. *F Page 6 of 16
Data Retention Characteristics
Over the Operating Range
Parameter Description Conditions Min Typ
[8]
Max Unit
V
DR
V
CC
for data retention 1.5 V
I
CCDR
[9]
Data retention current V
CC
= 1.5 V,
CE
1
> V
CC
– 0.2 V or CE
2
< 0.2 V or
(BHE
and BLE) > V
CC
– 0.2 V,
V
IN
> V
CC
– 0.2 V or V
IN
< 0.2 V
–0.87A
t
CDR
[10]
Chip deselect to data retention
time
0––ns
t
R
[11]
Operation recovery time 45 ns
Data Retention Waveform
Figure 3. Data Retention Waveform
[12, 13]
V
CC(min)
V
CC(min)
t
CDR
V
DR
> 1.5 V
DATA RETENTION MODE
t
R
V
CC
CE or
BHE
.BLE
Notes
8. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
CC
= V
CC(typ)
, T
A
= 25 °C.
9. Chip enables (CE
1
and CE
2
) need to be tied to CMOS levels to meet the I
SB1
/ I
SB2
/ I
CCDR
spec. Other inputs can be left floating.
10. Tested initially and after any design or process changes that may affect these parameters.
11. Full device operation requires linear V
CC
ramp from V
DR
to V
CC(min)
> 100 s or stable at V
CC(min)
> 100 s.
12. CE
refers to the internal logical combination of CE
1
and CE
2
such that when CE
1
is LOW and CE
2
is HIGH, CE is LOW. For all other cases CE is HIGH.
13. BHE
.BLE is the AND of both BHE and BLE. Deselect the chip by either disabling the chip enable signals or by disabling both BHE and BLE.

CY621472E30LL-45ZSXI

Mfr. #:
Manufacturer:
Cypress Semiconductor
Description:
SRAM 4Mb 3V 45ns 256K x 16 LP SRAM
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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