OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

MT46H64M32L2CG-5 IT:A TR

P1-P3P4-P6P7-P9P10-P12
PDF: 09005aef833913f1/Source: 09005aef833913d6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
ddr_mobile_sdram_only_152b_omap_pop.fm - Rev. E 06/09 EN
4 ©2008 Micron Technology, Inc. All rights reserved.
152-Ball x32 Mobile LPDDR (only) PoP (TI-OMAP)
General Description
General Description
Micron 152-ball packaged Mobile Low-Power DDR SDRAM (LPDDR) devices contain
either 1Gb LPDDR or 512Mb LPDDR die.
The 1Gb LPDDR die is a high-speed CMOS, dynamic random-access memory
containing 1,073,741,824 bits. It is internally configured as a quad-bank DRAM. Each of
the x32’s 268,435,456-bit banks is organized as 8192 rows by 1024 columns by 32 bits.
The 512Mb LPDDR die is a high-speed CMOS, dynamic random-access memory
containing 536,870,912 bits. It is internally configured as a quad-bank DRAM. Each of
the x32’s 134,217,728-bit banks is organized as 8192 rows by 512 columns by 32 bits.
Figure 2: Functional Block Diagram
RAS#
CAS#
Row-
address
MUX
CK
CS#
WE#
CK#
Control
logic
Column-
address
counter/
latch
Standard mode
register
Extended mode
register
Command
decode
Address,
BA0, BA1
CKE
Address
register
I/O gating
DM mask logic
Bank 0
memory
array
Bank 0
row-
address
latch
and
decoder
Bank
control
logic
Bank 1
Bank 2
Bank 3
Refresh
counter
32
2
2
32
32
4
Input
registers
4
4
4
4
RCVRS
4
64
64
8
64
CK
out
Data
DQS
Mask
Data
CK
CK
in
DRVRS
MUX
DQS
generator
32
32
32
32
32
64
DQ0–
DQ31
DQS0,
DQS1,
DQS2,
DQS3
4
Read
latch
Write
FIFO
and
drivers
1
COL 0
COL 0
Sense amplifiers
DM0,
DM1,
DM2,
DM3
CK
Column
decoder
PDF: 09005aef833913f1/Source: 09005aef833913d6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
ddr_mobile_sdram_only_152b_omap_pop.fm - Rev. E 06/09 EN
5 ©2008 Micron Technology, Inc. All rights reserved.
152-Ball x32 Mobile LPDDR (only) PoP (TI-OMAP)
Ball Assignments and Descriptions
Ball Assignments and Descriptions
Figure 3: 152-Ball VFBGA Ball Assignments
Notes: 1. Although not bonded to the die, these pins may be connected on the package substrate.
1
NC
NC
V
SSQ
DQ3
DQ0
V
SSQ
DQ4
DM0
V
DD
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
DNU
NC
1
2
NC
NC
DQS0
DQ5
DQ1
V
DDQ
DQ2
V
SS
NC
NC
NC
V
SS
NC
1
NC
V
SS
NC
1
NC
NC
NC
NC
NC
2
3
V
DDQ
DQ6
NC
NC
3
4
DM1
DQ7
NC
NC
4
5
DQ13
V
DDQ
NC
NC
5
6
DQ15
DQ9
V
SS
NC
1
6
7
V
SSQ
DQ14
NC
1
V
SS
7
8
DQ10
DQS1
NC
NC
8
9
DQ12
DQ11
NC
NC
9
10
DQ16
DQ8
NC
NC
10
11
DQ19
DQ17
V
SS
V
DD
11
12
CK
DQ18
RFU
TQ
12
13
V
SS
CK#
CKE1
V
SS
13
14
DM2
V
SSQ
V
DD
V
DDQ
14
15
V
DDQ
DQS2
CKE0
A13
15
16
DQ21
V
DD
A10
V
SSQ
16
17
DQ20
DQ23
V
SS
V
DD
17
18
DM3
DQ22
WE#
BA0
18
19
DQS3
DQ28
V
SSQ
V
DDQ
19
20
NC
NC
DQ24
DQ25
DQ27
V
SSQ
A0
V
SS
A2
A1
V
DDQ
A7
A8
V
SS
A5
CS1#
CAS#
BA1
V
SSQ
NC
NC
20
21
NC
NC
DQ26
DQ29
DQ31
V
DDQ
DQ30
V
DD
A3
A9
V
SSQ
A6
A11
V
DD
A12
CS0#
A4
RAS#
V
DDQ
DNU
NC
21
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
Top View – Ball Down
LPDDR Supply Ground
PDF: 09005aef833913f1/Source: 09005aef833913d6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
ddr_mobile_sdram_only_152b_omap_pop.fm - Rev. E 06/09 EN
6 ©2008 Micron Technology, Inc. All rights reserved.
152-Ball x32 Mobile LPDDR (only) PoP (TI-OMAP)
Ball Assignments and Descriptions
Notes: 1. Balls marked RFU may or may not be connected internally. These balls should not be used.
Contact factory for details.
Table 3: Ball Assignments
Symbol Type Description
A[13:0] Input
Address inputs: Specify the row or column address. Also used to load the mode registers. The
maximum address is determined by density and configuration. Consult the LPDDR product data
sheet for the maximum address for a given density and configuration. Unused address pins become
RFU.
1
BA0, BA1 Input
Bank address inputs: Specify one of the 4 banks.
CAS# Input
Column select: Specifies the command to execute.
CK, CK#
CK is the system clock. CK and CK# are differential clock inputs. All address and control signals are
sampled and referenced on the crossing of the rising edge of CK with the falling edge of CK#.
CKE0, CKE1 Input
Clock enable.
CKE0 is used for a single LPDDR product.
CKE1 is used for dual LPDDR products, and is considered RFU for single products.
CS0#, CS1# Input
Chip select:
CS0# is used for a single LPDDR product.
CS1# is used for dual LPDDR products, and is considered RFU for single products.
DM[3:0] Input
Data mask: Determines which bytes are written during WRITE operations.
RAS# Input
Row select: Specifies the command to execute.
WE# Input
Write enable: Specifies the command to execute.
DQ[31:0] Input/
output
Data bus: Data inputs/outputs.
DQS[3:0] Input/
output
Data strobe: Coordinates read/write transfers of data; one DQS per DQ byte.
TQ Output
Temperature sensor output: TQ HIGH when LPDDR T
J
exceeds 85°C.
V
DD
Supply
V
DD
: LPDDR power supply.
V
DDQ
Supply
V
DDQ
: LPDDR I/O power supply.
V
SSQ
Supply
V
SSQ
: LPDDR I/O ground.
RFU
1
–
Reserved for future use.
Table 4: Non-Device-Specific Ball Assignments
Symbol Type Description
V
SS
Supply
V
SS
: Shared ground.
DNU –
Do not use: Must be grounded or left floating.
NC –
No connect: Not internally connected.
P1-P3P4-P6P7-P9P10-P12

MT46H64M32L2CG-5 IT:A TR

Mfr. #:
Buy MT46H64M32L2CG-5 IT:A TR
Manufacturer:
Micron
Description:
IC DRAM 2G PARALLEL 152VFBGA
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet