www.fairchildsemi.com
REV. 1.2.3 December 2004
Features
±2.5% gain matching
±0.5 LSB linearity error
Internal bandgap voltage reference
•Low glitch energy
Single 3.3 Volt power supply
Applications
PC Graphics
•Video signal conversion
– RGB
YC
B
C
R
– Composite, Y, C
Description
The FMS3818 is a low-cost triple D/A converter, tailored to
fit graphics and video applications where speed is critical.
CMOS-level inputs are converted to analog current outputs
that can drive 25–37.5
loads corresponding to doubly-termi-
nated 50–75
loads. A sync current following SYNC
input
timing is added to the I
OG
output. BLANK
will override
RGB inputs, setting I
OG
, I
OB
and I
OR
currents to zero when
BLANK
= L. Although appropriate for many applications
the internal 1.25V reference voltage can be overridden by the
V
REF
input.
Few external components are required, just the current
reference resistor, current output load resistors, bypass
capacitors and decoupling capacitors.
Package is a 48-lead LQFP. Fabrication technology is
CMOS. Performance is guaranteed from 0 to 70°C.
Block Diagram
8 bit D/A
Converter
SYNC
8
SYNC
CLK
G
7-0
COMP
+1.25V
Ref
IO
G
I
OS
BLANK
8 bit D/A
Converter
8
B
7-0
IO
B
8 bit D/A
Converter
8
R
7-0
IO
R
R
REF
V
REF
FMS3818
Triple Video D/A Converters
3 x 8 bit, 180 Ms/s
FMS3818 DATA SHEET
2
REV. 1.2.3 December 2004
Functional Description
Within the FMS3818 are three identical 8-bit D/A
converters, each with a current source output. External loads
are required to convert these currents to voltage outputs.
Data inputs RGB
7-0
are overridden by the BLANK
input.
SYNC = H activates sync current from I
OS
for sync-on-
green video signals.
Figure 1. FMS3818 Current Source Structure
Digital Inputs
Incoming GBR data is registered on the rising edge of the
clock input, CLK. Analog outputs follow the rising edge of
CLK after a delay, t
DO
.
SYNC
and BLANK
SYNC
and BLANK inputs control the output level (Figure 1
and Table 1) of the D/A converters during CRT retrace
intervals. BLANK forces the D/A outputs to the blanking
level while SYNC = L turns off a current source, I
OS
that is
connected to the green D/A converter. SYNC
= H adds a
112/256 fraction of full-scale current to the green output.
SYNC = L extinguishes the sync current during the sync tip.
Figure 2. Nominal Output Levels
BLANK
gates the D/A inputs. If BLANK = H, the D/A
inputs control the output currents to be added to the output
blanking level. If BLANK = L, data inputs and the pedestal
are disabled.
D/A Outputs
Each D/A output is a current source from the V
DDA
supply.
Expressed in current units, the GBR transformation from
data to current is as
follows:
G = G
7-0
& BLANK
+ SYNC * 112
B = B
7-0
& BLANK
R = R
7-0
& BLANK
Typical LSB current step is 73.2 µA.
To obtain a voltage output, a resistor must be connected to
ground. Output voltage depends upon this external resistor,
the reference voltage, and the value of the gain-setting resis-
tor connected between R
REF
and GND.
To implement a doubly-terminated 75
transmission line, a
shunt 75
resistor should be placed adjacent to the analog
output pin. With a terminated 75
line connected to the
analog output, the load on the FMS3818 current source is
37.5
.
The FMS3818 may also be operated with a single 75 Ohm
terminating resistor. To lower the output voltage swing to the
desired range, the nominal value of the R
REF
resistor should
be doubled.
Voltage Reference
Full scale current is a multiple of the current I
SET
through an
external resistor, R
SET
connected between the R
REF
pin and
GND. Voltage across R
SET
is the reference voltage, V
REF
,
which can be derived from either the 1.25 volt internal
bandgap reference or an external voltage reference
connected to V
REF
. To minimize noise, a 0.1µF capacitor
should be connected between V
REF
and ground.
I
SET
is mirrored to each of the GBR output current sources.
To minimize noise, a 0.1µF capacitor should be connected
between the COMP pin and the analog supply voltage V
DDA
.
Power and Ground
Required power is a single +3.3 Volt supply. To minimize
power supply induced noise, analog +3.3V should be
connected to V
DDD
and V
DDA
pins with 0.1 and 0.01 µF
decoupling capacitors placed adjacent to each V
DD
pin or
pin pair.
High slew-rate digital data makes capacitive coupling to the
outputs of any D/A converter a potential problem. Since the
digital signals contain high-frequency components of the
CLK signal, as well as the video output signal, the resulting
data feedthrough often looks like harmonic distortion or
reduced signal-to-noise performance. All ground pins should
be connected to a common solid ground plane for best
performance.
V
DDA
SYNC
V
DDA
V
DDA
G
7-0
B
7-0
V
DDA
R
7-0
I
OS
data: 700 mV max.
sync: 307 mV
DATA SHEET FMS3818
REV. 1.2.3 December 2004
3
Table 1. Output Voltage Coding
V
REF
= 1.25 V, R
REF
= 348
, R
L
= 37.5
Pin Assignments
RGB7-0 (MSB…LSB) SYNC BLANK V
RED
, V
BLUE
(mV) V
GREEN
(mV)
1111 1111 1 1 700 1,007
1111 1111 0 1 700 700
1111 1110 1 1 697 1,004
1111 1101 1 1 695 1,001
1000 0000 1 1 351 658
0111 1111 1 1 349 656
0111 1111 0 1 349 349
0000 0010 1 1 5 312
0000 0001 1 1 3 310
0000 0000 1 1 0 307
0000 0000 0 1 0 0
XXXX XXXX 1 0 0 307
XXXX XXXX 0 0 0 0
GND
G
0
G
1
G
2
G
3
G
4
G
5
G
6
G
7
BLANK
V
DDD
R
0
GND
NC
R
REF
V
REF
COMP
IO
G
IO
R
V
DDA
V
DDA
IO
B
GND
GND
NC
GND
R
7
R
6
R
5
R
4
R
3
R
2
R
1
NC
GND
GND
B
0
B
1
B
2
B
3
B
4
B
6
B
5
NC
1
2
3
4
5
6
7
8
9
10
SYNC
11
12
36
35
34
33
32
31
30
29
28
27
CLK
26
25
13
14
15
16
17
18
19
20
21
22
B
7
23
24
48
47
46
45
44
43
42
41
40
39
GND
38
37
FMS3818
LQFP Package

FMS3818KRC

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
DAC 8BIT TRIPLE 180MHZ 48-LQFP
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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