FMS3818 DATA SHEET
4
REV. 1.2.3 December 2004
Pin Descriptions
Pin
Name Pin Number Value Pin Function Description
Clock and Data Inputs
CLK 26 CMOS
Clock Input.
Pixel data is registered on the rising edge of CLK. CLK
should be driven by a dedicated buffer to avoid reflection induced jitter,
overshoot, and undershoot.
R
7-0
G
7-0
B
7-0
47-40
9-2
23-16
CMOS
Red, Green, and Blue Pixel Data Inputs.
RGB digital inputs are
registered on the rising edge of CLK.
Controls
SYNC 11 CMOS
Sync Pulse Input.
Bringing SYNC LOW, disables a current source which
superimposes a sync pulse on the I
OG
output. SYNC and pixel data are
registered on the rising edge of CLK. SYNC does not override any other
data and should be used only during the blanking interval. If sync pulses
are not required, SYNC
should be connected to GND.
BLANK
10 CMOS
Blanking Input.
When BLANK is LOW, pixel data inputs are ignored and
the D/A converter outputs are driven to the blanking level. BLANK is
registered on the rising edge of CLK.
Video Outputs
I
OR
I
OG
I
OB
33
32
29
0.700 V
p-p
Red, Green, and Blue Current Outputs.
Current source outputs can
drive VESA VSIS, and RS-343A/SMPTE-170M compatible levels into
doubly-terminated 75 Ohm lines. Sync pulses can be added to the green
output. When SYNC
is HIGH, the current added to I
OG
is:
IO
S
= 2.33 (V
REF
/ R
REF
)
Voltage Reference
V
REF
35 +1.25 V
Voltage Reference Input/Output.
Internal 1.25V voltage reference is
available on this pin. An external +1.25 Volt reference may be applied to
this pin to override the internal reference. Decoupling V
REF
to GND with
a 0.1µF ceramic capacitor is required.
R
REF
36 348
Ω
Current-set Resistor Node.
Full-scale output current of each D/A
converter is determined by the value of the resistor connected between
R
REF
and GND. Nominal value of R
REF
is found from:
R
REF
= 5.31 (V
REF
/I
FS
)
where I
FS
is the full-scale output current (amps) from the
D/A converter (without sync). Sync is 0.439 I
FS
.
D/A full-scale current may also be calculated from:
I
FS
= V
FS
/R
L
Where V
FS
is the full-scale voltage level and R
L
is the total resistive load
(ohms) on each D/A converter.
COMP 34 0.1 µF
Compensation Capacitor Node.
A 0.1 µF ceramic capacitor must be
connected between COMP and V
DD
to stabilize internal bias circuitry.
