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MK2049-34SAI

P1-P3P4-P6P7-P9
DATASHEET
3.3 VOLT COMMUNICATIONS CLOCK VCXO PLL MK2049-34A
IDT™
3.3 VOLT COMMUNICATIONS CLOCK VCXO PLL 1
MK2049-34A REV D 121809
Description
The MK2049-34A is a VCXO Phased Locked Loop (PLL)
based clock synthesizer that accepts multiple input
frequencies. With an 8 kHz clock input as a reference, the
MK2049-34A generates T1, E1, T3, E3, ISDN, xDSL, and
other communications frequencies. This allows for the
generation of clocks frequency-locked and phase-locked to
an 8 kHz backplane clock, simplifying clock synchronization
in communications systems. The MK2409-34 can also
accept a T1 or E1 input clock and provide the same output
for loop timing. All outputs are frequency locked together
and to the input.
This part also has a jitter-attenuated Buffer capability. In this
mode, the MK2049-34A is ideal for filtering jitter from 27
MHz video clocks or other clocks with high jitter.
IDT can customize these devices for many other different
frequencies.
Features
• Packaged in 20-pin SOIC
• Available in Pb (lead) free package
• 3.3 V + 5% operation
• Fixed I/O phase relationship on all selections
• Meets the TR62411, ETS300 011, and GR-1244
specification for MTIE, Pull-in/Hold-in Range, Phase
Transients, and Jitter Generation for Stratum 3, 4, and 4E
• Accepts multiple inputs: 8 kHz backplane clock, Loop
Timing frequencies, or 10 to 36 MHz
• Locks to 8 kHz + 100 ppm (External mode)
• Buffer Mode allows jitter attenuation of 10 to 36 MHz
input and x1/x0.5 or x2/x4 outputs
• Exact internal ratios enable zero ppm error
• Output clock rates include T1, E1, T3, E3, ISDN, xDSL,
and the OC3 submultiples
• See the MK2049-01, -02, and -03 for more selections at
5 V
• Industrial temperature range
NOTE: EOL for non-green parts to occur on 5/13/10
per PDN U-09-01
Block Diagram
VCXO-BASED
PLL
(M
ASTER CLOCK
GENERATOR)
EXTERNAL PULLABLE CRYSTAL
(external loop filter)
FREQUENCY
MULTIPLYING
PLL
2
INPUT REFERENCE
CLOCK
(TYPICALLY 8KHZ)
C
LOCK OUTPUT
CLOCK OUTPUT / 2
8
KHZ (REGENERATED)
4
F
REQUENCY SELECT
MK2049-34A
3.3 VOLT COMMUNICATIONS CLOCK VCXO PLL VCXO AND SYNTHESIZER
IDT™ /
3.3 VOLT COMMUNICATIONS CLOCK VCXO PLL 2
MK2049-34A REV D 121809
Pin Assignment
20-pin (300) mil SOIC
Pin Descriptions
16
1
15
2
14
FS1 FS0
3
13
X2
4
12
X1
RES
5
11
VDD
6
CAP2
7
FCAP
8
VDD
GND
CAP1
VDD
GND
GND
CLK
ICLK
9
10
CLK/2
FS3
8k
FS2
20
19
18
17
Pin
Number
Pin
Name
Pin
Type
Pin Description
1 FS1 Input Frequency select 1. Determines CLK input/outputs per table on page 3.
2 X2 XO Crystal connection. Connect to a MHz crystal as shown in table on page 3.
3 X1 XI Crystal connection. Connect to a MHz crystal as shown in table on page 3.
4 VDD Power Power supply. Connect to +3.3 V.
5 FCAP — Filter capacitor. Connect a 1000 pF ceramic capacitor to ground.
6 VDD Power Power supply. Connect to +3.3 V.
7 GND Power Connect to ground
8 CLK Output Clock output determined by status of FS3:0 per tables on page 3.
9 CLK/2 Output Clock output determined by status of FS3:0 per tables page 3. Always 1/2 of
CLK.
10 8k Output Recovered 8 kHz clock output.
11 FS2 Input Frequency select 2. Determines CLK input/outputs per tables on page 3.
12 FS3 Input Frequency select 3. Determines CLK input/outputs per tables on page 3.
13 ICLK Input Input clock connection. Connect to 8 kHz backplane or MHz clock.
14 GND Power Connect to ground.
15 VDD Power Power Supply. Connect to +3.3 V.
16 CAP1 Loop
Filter
Connect the loop filter ceramic capacitors and resistor between this pin and
CAP2.
17 GND Power Connect to ground.
18 CAP2 Loop Connect the loop filter ceramic capacitors and resistor between this pin and
19 RES — Connect a 10-200kΩ resistor to ground. Contact IDT for recommended value
for your application.
20 FS0 Input Frequency select 0. Determines CLK input/outputs per table on page 3.
MK2049-34A
3.3 VOLT COMMUNICATIONS CLOCK VCXO PLL VCXO AND SYNTHESIZER
IDT™ /
3.3 VOLT COMMUNICATIONS CLOCK VCXO PLL 3
MK2049-34A REV D 121809
Output Decoding Table - External Mode (MHz)
Output Decoding Table - Loop Timing Mode (MHz)
Output Decoding Table - Buffer Mode (MHz)
0 = connect directly to ground, 1 = connect directly to VDD
Crystal is connected to pins 2 and 3; clock input is applied to pin 13.
Operating Modes
The MK2049-34A has three operating modes: External, Loop Timing, and Buffer. Although each mode uses an input clock
to generate various output clocks, there are important differences in their input and crystal requirements.
External Mode
The MK2049-34 accepts an external 8 kHz clock and will produce a number of common communication clock frequencies.
The 8 kHz input clock does not need to have a 50% duty cycle; a “high” or “on” pulse as narrow as 10 ns is acceptable. In
the MK2049-34, the rising edges of CLK and CLK/2 are both aligned with the rising edge of the 8 kHz ICLK; refer to Figure
1 on page 4 for more details.
Loop Timing Mode
This mode can be used to remove the jitter from standard high-frequency communication clocks. For T1 and E1 inputs, the
CLK/2 output will be the same as the input frequency, with CLK at twice the input frequency.
ICLK FS3 FS2 FS1 FS0 CLK/2 CLK 8k
Crystal
Used (MHz) N
8 kHz00001.5443.0888 kHz12.352 1544
8 kHz00012.0484.0968 kHz12.288 1536
8 kHz001022.36844.7368 kHz11.184 1398
8 kHz001117.18434.3688 kHz11.456 1432
8 kHz010019.4438.888 kHz 9.72 1215
8 kHz010116.38432.7688 kHz 8.192 1024
8 kHz011017.66435.3288 kHz17.664 2208
8 kHz011118.68837.3768 kHz 9.344 1168
8 kHz1010 7.68 15.368 kHz 15.36 1920
8 kHz101110.75221.5048 kHz10.752 1344
8 kHz110010.2420.488 kHz 10.24 1280
8 kHz110138.8877.768 kHz 9.72 1215
ICLK FS3 FS2 FS1 FS0 CLK/2 CLK 8k Crystal N
1.54410001.5443.088N/A12.35224
2.04810012.0484.096N/A12.28818
ICLK FS3 FS2 FS1 FS0 CLK/2 CLK 8k Crystal N
19 - 361110ICLK/2ICLKN/AICLK/23
10 - 1811112*ICLK4*ICLKN/AICLK 3
P1-P3P4-P6P7-P9

MK2049-34SAI

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IC VCXO PLL CLK SYNTH 20-SOIC
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