MK2049-34SAI Datasheet MK2049-34SAI, MK2049-34SAILF, MK2049-34SAILFTR | P4-P6

MK2049-34A

3.3 VOLT COMMUNICATIONS CLOCK VCXO PLL VCXO AND SYNTHESIZER

IDT™ /

3.3 VOLT COMMUNICATIONS CLOCK VCXO PLL 4

MK2049-34A REV D 121809

Buffer Mode

Unlike the other two modes that accept only a single specified input frequency, Buffer Mode will accept a wider range of

input clocks. The input jitter is attenuated and the outputs on CLK and CLK/2 also provide the option of getting x1, x2, x4, or

1/2 of the input frequency. For example, this mode can be used to remove the jitter from a 27 MHz clock, generating

low-jitter 27 MHz and 13.5 MHz outputs.

Input and Output Synchronization

As shown in the tables on page 3, the MK2049-34A offers a Zero Delay feature in all selections. There is an internal

feedback path between ICLK and the output clocks, providing a fixed phase relationship between the input and output, a

requirement in many communication systems.

The rising edge of ICLK will be aligned with the rising edges of CLK and CLK/2 (8 kHz is used in this illustration, but the

same is true for the selections in the Loop Timing and Buffer Modes).

Measuring Zero Delay on the MK2049

The MK2049-34 produces low-jitter output clocks. In addition, this part has a very low bandwidth on the order of a few Hertz.

Since most 8 kHz input clocks will have high jitter, this can make measuring the input-to-output skew (zero delay feature)

very difficult. The MK2049 is designed to reject the input jitter; when the input and output clocks are both displayed on an

oscilloscope, they may appear not to be locked because the scope trigger point is constantly changing with the input jitter.

In fact, the input and output clocks probably are locked and the MK2049 will have zero delay to the average

position of the

8 kHz input clock. In order to see this clearly, a low jitter 8 kHz input clock is necessary. Most lab frequency sources are NOT

SUITABLE for this since they have high jitter at low frequencies.

Frequency Locking to the Input

In all modes, the output clocks are frequency-locked to the input. The outputs will remain at the specified output frequency

as long as the combined variation of the input frequency and the crystal does not exceed 100 ppm. For example, if the

crystal can vary ±40 ppm (initial accuracy + temperature + aging), then the input frequency can vary by up to 60 ppm and

still have the output clock remain frequency-locked.

IC LK (8 kH z)

CLK (MHz)

CLK/2 (MHz)

Figure 1. MK2049-34 Input and Output Clock Waveforms

MK2049-34A

3.3 VOLT COMMUNICATIONS CLOCK VCXO PLL VCXO AND SYNTHESIZER

IDT™ /

3.3 VOLT COMMUNICATIONS CLOCK VCXO PLL 5

MK2049-34A REV D 121809

PC Board Layout

A proper board layout is critical to the successful use of the MK2049-34A. In particular, the CAP1 and CAP2 pins are very

sensitive to noise and leakage (CAP2 at pin 18 is the most sensitive). Traces must be as short as possible and the two

capacitors and resistor must be mounted next to the device as shown below. The capacitor shown between pins 15 and 17,

and the one between pins 4 and 7 are the power supply decoupling capacitors. The high frequency output clocks on pins 8

and 9 should have a series termination of 33Ω connected close to the pin. Additional improvements will come from keeping

all components on the same side of the board, minimizing vias through other signal layers, and routing other signals away

from the MK2049. You may also refer to application note MAN05 for additional suggestions on layout of the crystal selection.

The crystal traces should include pads for small capacitors from X1 and X2 to ground. These are used to adjust the stray

capacitance of the board to match the crystal load capacitance. The typical telecom reference frequency is accurate to

much less than 1 ppm, so the MK2049-34A may lock and run properly even if the board capacitance is not adjusted with

these fixed capacitors. However, IDT recommends that the adjustment capacitors be included to minimize the effects of

variation in individual crystals, temperature, and aging. The value of these capacitors (typically 0 - 4 pF) is determined once

for a given board layout, using the procedure found in application note MAN05.

cap

resist

cap

resist

cap

Optional -

see text

Cutout in ground and power plane.

Route all traces away from this area.

= connect to VDD

= connect to GND

Figure 2. Typical MK2049-34 Layout

MK2049-34A

3.3 VOLT COMMUNICATIONS CLOCK VCXO PLL VCXO AND SYNTHESIZER

IDT™ /

3.3 VOLT COMMUNICATIONS CLOCK VCXO PLL 6

MK2049-34A REV D 121809

External Component Selection

The MK2049-34A requires a minimum number of external components for proper operation. Decoupling capacitors of

0.01µF must be connected between VDD and GND pins close to the chip (especially pins 4 and 7, 15 and 17), and 33Ω

series terminating resistors should be used on clock outputs with traces longer than one inch (assuming 50Ω traces). The

selection of additional external components is described in the following sections.

Loop Filter

Information on how to configure the external loop filter, connected between pins CAP1 and CAP2, can be found on the IDT

web site.

Crystal Operation

The MK2049-34A operates by phase locking the input signal to a VCXO which consists of the recommended pullable VCXO

crystals and the integrated VCXO oscillator circuit on the MK2049-34A. To achieve the best performance and reliability, the

layout guidelines shown on the previous page should be closely followed.

The frequency of oscillation of a quartz crystal is determined by its cut and by the load capacitors connected to it. The

MK2049-34A has variable load capacitors on-chip which “pull” or change the frequency of the crystal. External stray

capacitance must be kept to a minimum to ensure maximum pullability of the crystal. To achieve this, the layout should use

short traces between the MK2049-34A and the crystal.

For the VCXO to operate correctly, a pullable crystal must be used. For more information, including a list of approved

crystals, please refer to application note MAN05.

Absolute Maximum Ratings

Stresses above the ratings listed below can cause permanent damage to the MK2049-34A. These ratings, which

are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at

these or any other conditions above those indicated in the operational sections of the specifications is not implied.

Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical

parameters are guaranteed only over the recommended operating temperature range.

Recommended Operation Conditions

Item Rating

Supply Voltage, VDD 7 V

All Inputs and Outputs -0.5 V to VDD+0.5 V

Ambient Operating Temperature -40 to +85° C

Storage Temperature -65 to +150° C

Junction Temperature 175° C

Soldering Temperature 260° C (10 to 20 seconds max.)

Parameter Min. Typ. Max. Units

Ambient Operating Temperature -40 +85 ° C

Power Supply Voltage (measured in respect to GND) +3.15 +3.3 +3.45 V

P1-P3 P4-P6 P7-P9

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