13
Test Circuit Diagrams
Unless otherwise noted, all test circuits are at T
A
= 25°C, V
CC1
= 5 V, V
CC2
= 5 V, sinusoidal waveform input, and signal
frequency f = 132 kHz.
100 nF
GND2
100 nF
SCOPE
100 µF
V
CC2
1 µF
V
CC1
1 µF
GND2
GND1
100 nF
HCPL-800J
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Tx-en
Tx-in
Rx-PD-out
Rx-Amp-in
Status
Rx-out
V
CC1
GND1
R
ref
Rx-in
C
ext
Tx-LD-in
Tx-PD-out
V
CC2
Tx-out
GND2
V
IN
= 1.5 V
PP
24 kÙ
R
ref
2.5 Ù
R
L
GND2
V
CC1
100 nF
GND2
100 nF
5 V
GND1
HCPL-800J
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Tx-en
Tx-in
Rx-PD-out
Rx-Amp-in
Status
Rx-out
V
CC1
GND1
R
ref
Rx-in
C
ext
Tx-LD-in
Tx-PD-out
V
CC2
Tx-out
GND2
100 nF
V
CC1
24 kÙ
R
ref
V
OUT
SCOPE
100 nF
100 nF
1 µF
100 µF
GND1
V
IM
= 10 V
PP
GND1
1 kÙ
HCPL-800J
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Tx-en
Tx-in
Rx-PD-out
Rx-Amp-in
Status
Rx-out
V
CC1
GND1
R
ref
Rx-in
C
ext
Tx-LD-in
Tx-PD-out
V
CC2
Tx-out
GND2
100 µF
V
CC2
100 nF
2 kÙ
V
IN
= 0.5 V
PP
24 kÙ
R
ref
V
CC1
100 nF
GND2
GND2
PULSE GEN.
GND1
100 nF
GND1
100 nF
1 µF
V
OUT
V
PULSE
= 5 V,
f
PULSE
¼
1 kHz
Figure 19. Load detection test circuit
Figure 20. Isolation mode rejection ratio test circuit
Figure 21. Tx-PD-out enable/ disable time test circuit
14
Test Circuit Diagrams (Cont.)
Unless otherwise noted, all test circuits are at T
A
= 25°C, V
CC1
= 5 V, V
CC2
= 5 V, sinusoidal waveform input, and signal
frequency f = 132 kHz.
100 nF
1 µF
SPECTRUM
100 nF
V
CC2
HCPL-800J
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Tx-en
Tx-in
Rx-PD-out
Rx-Amp-in
Status
Rx-out
V
CC1
GND1
R
ref
Rx-in
C
ext
Tx-LD-in
Tx-PD-out
V
CC2
Tx-out
GND2
V
CC1
24 kÙ
R
ref
1 µF
GND1
100 µF
100 nF
GND2
50 Ù
GND2
2 kÙ
V
IN
= 0.5 V
PP
ANALYZER
100 nF
V
CC1
1 kÙ
GND2
GND2
100 µF
SPECTRUM
ANALYZER
V
IN
24 kÙ
R
ref
GND1
2 kÙ
HCPL-800J
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Tx-en
Tx-in
Rx-PD-out
Rx-Amp-in
Status
Rx-out
V
CC1
GND1
R
ref
Rx-in
C
ext
Tx-LD-in
Tx-PD-out
V
CC2
Tx-out
GND2
100 nF
100 nF
100 nF
V
CC2
50 Ù
V
CC1
V
CC1
GND2
100 nF
1 µF
100 nF
GND1
1 µF
V
OUT
= 3.6 V
PP
V
IN
= 1 V
PP
f = 10 k ~ 10 MHz
100 nF
100 µF
GND1
50 Ù
R
L
24 kÙ
R
ref
V
OUT
100 nF
GND2
GND2
100 nF
1 µF
1 µF
HCPL-800J
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Tx-en
Tx-in
Rx-PD-out
Rx-Amp-in
Status
Rx-out
V
CC1
GND1
R
ref
Rx-in
C
ext
Tx-LD-in
Tx-PD-out
V
CC2
Tx-out
GND2
100 nF
2 kÙ
V
CC1
V
CC2
V
CC1
100 nF
GND1
GND2
Figure 22. Tx-PD-out harmonic distortion test circuit
Figure 23. Line driver harmonic distortion test circuit
Figure 24. Line driver bandwidth test circuit
15
100 nF
Filter
100 µF
V
CC2
GND2
R
ref
24 kÙ
C2
X2
GND2
N
C1
100 nF
GND2
Status
D1
R4
2 Ù
100 nF
V
CC1
100 nF
GND2
1 µF
R1
5 kÙ
GND2
Rx-out
GND1
Filter
1 µF
GND1
Tx-en
Tx
-in
L2
R3
2 kÙ
R2
10 kÙ
L
L1
330 µH
GND2
HCPL-800J
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Tx-en
Tx-in
Rx-PD-out
Rx-Amp-in
Status
Rx-out
V
CC1
GND1
R
ref
Rx-in
C
ext
Tx-LD-in
Tx-PD-out
V
CC2
Tx-out
GND2
Figure 25. Schematic of HCPL - 800J application for FSK modulation scheme
Applications Information
Typical application for FSK modulation scheme
The HCPL-800J is designed to work with various trans-
ceivers and can be used with a variety of modulation
methods including ASK, FSK and BPSK. Figure 25 shows
a typical application in a powerline modem using
Frequency Shift Keying (FSK) modulation scheme.
Transmitter
The analogue Tx input pin is connected to the modulator
via an external coupling capacitor C1 and a series resistor
R3 (see Figure 25). Optimal performance is obtained with
an input signal of 250 µA
PP
. E.g., for a modulator with an
output signal of 0.5 V
PP
using a coupling capacitor of 100
nF, the optimal series resistor R3 would be 2 k.
TX AGC
To ensure a stable and constant output voltage at Tx-PD-
out, the HCPL-800J includes an Automatic Gain Control
(AGC) circuit in the isolated transmit signal path.
This AGC circuit compensates for variations in the
input signal level presented at Tx-in and variations in
the optical channel over temperature and time. The
Tx-PD-out output signal is effectively stabilized for input
Tx-in signals of between 150 µA
PP
and 250 µA
PP
(see
Figure 8). The AGC circuit starts to function 10 µs after the
Tx-en signal is set to logic high. After a period of 180 µs
the Tx-PD-out signal typically reaches 66% of its steady
state level (see Figure 26). To ensure correct operation of
the internal circuitry, an external 1 µF capacitor needs to
be connected from pin 11 to GND2.
The optical signal coupling technology used in the
HCPL-800J transmit path achieves very good harmonic
distortion typically HD2 < -50 dB and HD3 < -62 dB, which
is usually significantly better than the distortion perfor-
mance of the modulated input signal. However to meet
the requirements of some international EMC regulations
it is often necessary to filter the modulated input signal.
The optimal position for such a filter is between pins 13
and 12 as shown in Figure 25. A possible band-pass filter
topology is shown in Figure 27, some typical values of
the components in this filter are listed in Table 1.
Figure 26. Tx-PD-out AGC response time
5 0 µs/Div
Tx-en 5 V/Div
Tx-PD-out 1 V/Div
t
s, Tx
t
AGC

HCPL-800J-500

Mfr. #:
Manufacturer:
Broadcom / Avago
Description:
Buffers & Line Drivers PLC Powerline DAA IC
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet