10
FN8113.2
June 30, 2008
Absolute Maximum Ratings Thermal Information
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . .-65°C to +135°C
Voltage on any Pin with Respect to V
SS
. . . . . . . . . . . . -1.0V to +7V
DC Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Commerical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
Industrial. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
DC Operating Characteristics Over the recommended operating conditions unless otherwise specified.
SYMBOL PARAMETER TEST CONDITIONS
V
CC
= 1.8 TO 3.6V V
CC
= 2.7 TO 5.5V
UNITMIN MAX MIN MAX
I
CC
(Note 1)
Active Supply Current Read Control
Register
f
SCL
= 400kHz nonvolatile,
SDA = Open
0.5 1.0 mA
I
CC2
(Note 1)
Active Supply Current Write Control
Register
f
SCL
= 400kHz nonvolatile,
SDA = Open
1.5 3.0 mA
I
CC3
(Note 2)
Operating Current AC (WDT Off) f
SCL
= 400kHz nonvolatile,
SDA = Open
11µA
I
CC4
(Note 2)
Operating Current DC (WDT Off) V
SDA
= V
SCL
= V
CC
Others = GND or V
SB
11µA
I
CC5
(Note 2)
Operating Current DC (WDT On) V
SDA
= V
SCL
= V
CC
Others = GND or V
SB
10 20 µA
I
LI
Input Leakage Current V
IN
= GND to V
CC
10 10 µA
I
LO
Output Leakage Current V
SDA
= GND to V
CC
Device is in Standby
(Note 2)
10 10 µA
V
IL
(Note 3)
Input LOW Voltage -0.5 V
CC
x 0.3 -0.5 V
CC
x 0.3 V
V
IH
(Note 3)
Input HIGH Voltage V
CC
x 0.7 V
CC
+ 0.5 V
CC
x 0.7 V
CC
+ 0.5 V
V
HYS
Schmitt Trigger Input Hysteresis
Fixed Input Level 0.2 0.2 V
V
CC
Related Level 0.05 x V
CC
0.05 x V
CC
V
V
OL
Output LOW Voltage I
OL
= 3.0mA (2.7V to 5.5V)
I
OL
= 1.8mA (1.8V to 3.6V)
0.4 0.4 V
NOTES:
1. The device enters the active state after any start, and remains active until: 9 clock cycles later if the device select bits in the slave address byte
are incorrect; 200ns after a stop ending a read operation; or t
WC
after a stop ending a write operation.
2. The device goes into standby: 200ns after any stop, except those that initiate a nonvolatile write cycle; t
WC
after a stop that initiates a nonvolatile
cycle; or 9 clock cycles after any start that is not followed by the correct device select bits in the slave address byte.
3. V
IL
min. and V
IH
max. are for reference only and are not tested.
Capacitance (T
A
= +25°C, f = 1.0 MHz, V
CC
= 5V)
SYMBOL PARAMETER TYP UNIT TEST CONDITIONS
C
OUT
Output Capacitance (SDA, RESET/RESET) 8 pF V
OUT
= 0V
C
IN
Input Capacitance (SCL, WP) 6 pF V
IN
= 0V
X4003, X4005
11
FN8113.2
June 30, 2008
Equivalent AC Load Circuit
AC Test Conditions
5V
4.6k
RESET
100pF
SDA
1533
100pF
5V
For V
OL
= 0.4V
and I
OL
= 3mA
RESET
Input pulse levels 0.1V
CC
to 0.9V
CC
Input rise and fall times 10ns
Input and output timing levels 0.5V
CC
Output load Standard output load
AC Electrical Specifications Over recommended operating conditions, unless otherwise specified.
SYMBOL PARAMETER
100kHz 400kHz
UNITMIN MAX MIN MAX
f
SCL
SCL Clock Frequency 0 100 0 400 kHz
t
IN
Pulse Width Suppression Time at Inputs n/a n/a 50 ns
t
AA
SCL LOW to SDA Data Out Valid 0.1 0.9 0.1 0.9 µs
t
BUF
Time the Bus Free Before Start of New Transmission 4.7 1.3 µs
t
LOW
Clock LOW Time 4.7 1.3 µs
t
HIGH
Clock HIGH Time 4.0 0.6 µs
t
SU:STA
Start Condition Set-up Time 4.7 0.6 µs
t
HD:STA
Start Condition Hold Time 4.0 0.6 µs
t
SU:DAT
Data in Setup Time 250 100 ns
t
HD:DAT
Data in Hold Time 5.0 0 µs
t
SU:STO
Stop Condition Set-up Time 0.6 0.6 µs
t
DH
Data Output Hold Time 50 50 ns
t
R
SDA and SCL Rise Time 1000 20 + 0.1Cb
(Note 5)
300 ns
t
F
SDA and SCL Fall Time 300 20 + 0.1Cb
(Note 5)
300 ns
t
SU:WP
WP Set-up Time 0.4 0.6 µs
t
HD:WP
WP Hold Time 0 0 µs
Cb Capacitive Load for Each Bus Line 400 400 pF
NOTES:
4. Typical values are for T
A
= +25°C and V
CC
= 5.0V
5. Cb = total capacitance of one bus line in pF
X4003, X4005
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FN8113.2
June 30, 2008
Timing Diagrams
Bus Timing
WP Pin Timing
Write Cycle Timing
t
SU:STO
t
DH
t
HIGH
t
SU:STA
t
HD:STA
t
HD:DAT
t
SU:DAT
SCL
SDA IN
SDA OUT
t
F
t
LOW
t
BUF
t
A
t
R
t
HD:WP
SCL
SDA IN
WP
t
SU:WP
CLK 1 CLK 9
SLAVE ADDRESS BYTE
START
SCL
SDA
t
WC
8
TH
BIT OF LAST BYTE ACK
STOP
CONDITION
START
CONDITION
Nonvolatile Write Cycle Timing
SYMBOL PARAMETER MIN
TYP
(Note 1) MAX UNIT
t
WC
(Note 6) Write Cycle Time 5 10 ms
NOTE:
6. t
WC
is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is the
minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.
X4003, X4005

X4005S8IZ-2.7A

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Supervisory Circuits CPU SUP/WDT I2CS HI 6V IND 2 93VTRIP
Lifecycle:
New from this manufacturer.
Delivery:
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