X4005S8IZ-2.7A Datasheet X4005S8IZ, X4003S8IZ, X4003M8IZ | P7-P9

FN8113.2

June 30, 2008

WEL: Write Enable Latch (Volatile)

The WEL bit controls the access to the control register

during a write operation. This bit is a volatile latch that

powers up in the LOW (disabled) state. While the WEL bit is

LOW, writes the control register will be ignored (no

acknowledge will be issued after the data byte). The WEL bit

is set by writing a “1” to the WEL bit and zeroes to the other

bits of the control register. Once set, WEL remains set until

either it is reset to 0 (by writing a “0” to the WEL bit and

zeroes to the other bits of the control register) or until the

part powers up again. Writes to the WEL bit do not cause a

nonvolatile write cycle, so the device is ready for the next

operation immediately after the stop condition.

WD1, WD0: Watchdog Timer Bits

The bits WD1 and WD0 control the period of the watchdog

timer. The options are shown in the following:

Writing to the Control Register

Changing any of the nonvolatile bits of the control register

requires the following steps:

• Write a 02H to the control register to set the write enable

latch (WEL). This is a volatile operation, so there is no

delay after the write. (Operation preceeded by a start and

ended with a stop.)

• Write a 06H to the control register to set both the register

write enable latch (RWEL) and the WEL bit. This is also a

volatile cycle. The zeros in the data byte are required.

(Operation preceeded by a start and ended with a stop.)

• Write a value to the control register that has all the control

bits set to the desired state. This can be represented as

0xy0 0010 in binary, where xy are the WD bits. (Operation

preceeded by a start and ended with a stop.) Since this is

a nonvolatile write cycle it will take up to 10ms to

complete. The RWEL bit is reset by this cycle and the

sequence must be repeated to change the nonvolatile bits

again. If bit 2 is set to ‘1’ in this third step (0xy0 0110) then

the RWEL bit is set, but the WD1 and WD0 bits remain

unchanged. Writing a second byte to the control register is

not allowed. Doing so aborts the write operation and

returns a NACK.

• A read operation occurring between any of the previous

operations will not interrupt the register write operation.

• The RWEL bit cannot be reset without writing to the

nonvolatile control bits in the control register, power

cycling the device or attempting a write to a write

protected block.

To illustrate, a sequence of writes to the device consisting of

[02H, 06H, 02H] will reset all of the nonvolatile bits in the

control register to 0. A sequence of [02H, 06H, 06H] will

leave the nonvolatile bits unchanged and the RWEL bit

remains set.

Serial Interface

Serial Interface Conventions

The device supports a bidirectional bus oriented protocol.

The protocol defines any device that sends data onto the

bus as a transmitter, and the receiving device as the

receiver. The device controlling the transfer is called the

master and the device being controlled is called the slave.

The master always initiates data transfers, and provides the

clock for both transmit and receive operations. Therefore,

the devices in this family operate as slaves in all

applications.

Serial Clock and Data

Data states on the SDA line can change only during SCL

LOW. SDA state changes during SCL HIGH are reserved for

indicating start and stop conditions. See Figure 6.

WD1 WD0 WATCHDOG TIME-OUT PERIOD

0 0 1.4s

0 1 600ms

1 0 200ms

1 1 Disabled (factory setting)

SCL

DATA STABLE DATA CHANGE DATA STABLE

SDA

FIGURE 6. VALID DATA CHANGES ON THE SDA BUS

X4003, X4005

FN8113.2

June 30, 2008

Serial Start Condition

All commands are preceded by the start condition, which is a

HIGH to LOW transition of SDA when SCL is HIGH. The

device continuously monitors the SDA and SCL lines for the

start condition and will not respond to any command until

this condition has been met. See Figure 7.

Serial Stop Condition

All communications must be terminated by a stop condition,

which is a LOW to HIGH transition of SDA when SCL is

HIGH. The stop condition is also used to place the device

into the Standby power mode after a read sequence. A stop

condition can only be issued after the transmitting device

has released the bus. See Figure 7.

Serial Acknowledge

Acknowledge is a software convention used to indicate

successful data transfer. The transmitting device, either

master or slave, will release the bus after transmitting eight

bits. During the ninth clock cycle, the receiver will pull the

SDA line LOW to acknowledge that it received the eight bits

of data. Refer to Figure 8.

The device will respond with an acknowledge after

recognition of a start condition and the correct contents of

the slave address byte. Acknowledge bits are also provided

by the X4003/4005 after correct reception of the control

control register and after the second slave address in a read

question (see Figures 9 and 10).

Serial Write Operations

Slave Address Byte

Following a start condition, the master must output a slave

address byte. This byte consists of several parts:

• a device type identifier that is always ‘1011’.

• two bits of ‘0’.

• one bit of the slave command byte is a R/W

bit. The R/W

bit of the slave address byte defines the operation to be

SCL

SDA

START STOP

FIGURE 7. VALID START AND STOP CONDITIONS

DATA OUTPUT

FROM

TRANSMITTER

DATA OUTPUT

FROM RECEIVER

81 9

START

ACKNOWLEDGE

SCL FROM

MASTER

FIGURE 8. ACKNOWLEDGE RESPONSE FROM RECEIVER

SLAVE

ADDRESS

BYTE

ADDRESS

DATA

SDA BUS

SIGNALS

FROM THE

SLAVE

SIGNALS

FROM THE

MASTER

START

STOP

100110111111111

FIGURE 9. WRITE CONTROL REGISTER SEQUENCE

X4003, X4005

FN8113.2

June 30, 2008

performed. When the R/W bit is a one, then a read

operation is selected. A zero selects a write operation.

Refer to Figure 9.

• After loading the entire slave address byte from the SDA

bus, the device compares the input slave byte data to the

proper slave byte. Upon a correct compare, the device

outputs an acknowledge on the SDA line.

Write Control Register

To write to the control register, the device requires the slave

address byte and a byte address. This gives the master

access to register. After receipt of the address byte, the

device responds with an acknowledge, and awaits the data.

After receiving the 8 bits of the data byte, the device again

responds with an acknowledge. The master then terminates

the transfer by generating a stop condition, at which time the

device begins the internal write cycle to the nonvolatile memory.

During this internal write cycle, the device inputs are disabled,

so the device will not respond to any requests from the master.

If WP is HIGH, the control register cannot be changed. A write

to the control register will suppress the acknowledge bit and no

data in the control register will change. With WP low, a second

byte written to the control register terminates the operation and

no write occurs.

Stops and Write Modes

Stop conditions that terminate write operations must be sent by

the master after sending 1 full data byte plus the subsequent

ACK signal. If a stop is issued in the middle of a data byte, or

before 1 full data byte plus its associated ACK is sent, then the

device will reset itself without performing the write.

Serial Read Operations

The read operation allows the master to access the control

C standard, prior to issuing the

slave address byte with the R/W

bit set to one, the master

must first perform a “dummy” write operation. The master

issues the start condition and the slave address byte,

receives an acknowledge, then issues the byte address.

After acknowledging receipt of the byte address, the master

immediately issues another start condition and the slave

address byte with the R/W

bit set to one. This is followed by

an acknowledge from the device and then by the eight bit

control register. The master terminates the read operation by

not responding with an acknowledge and then issuing a stop

condition. Refer to Figure 10 for the address, acknowledge,

and data transfer sequences.

Operational Notes

The device powers-up in the following state:

• The device is in the low power standby state.

• The WEL bit is set to ‘0’. In this state it is not possible to

write to the device.

• SDA pin is the input mode.

RESET

/RESET signal is active for t

PURST

Data Protection

The following circuitry has been included to prevent

inadvertent writes:

• The WEL bit must be set to allow a write operation.

• The proper clock count and bit sequence is required prior

to the stop bit in order to start a nonvolatile write cycle.

• A three step sequence is required before writing into the

control register to change watchdog timer or block lock

settings.

• The WP pin, when held HIGH, prevents all writes to the

control register.

• Communication to the device is inhibited below the V

TRIP

voltage.

• Command to change the control register are terminated if

in-progress when RESET

/RESET go active.

Symbol Table

WAVEFORM INPUTS OUTPUTS

Must be

steady

Will be

steady

May change

from LOW

to HIGH

Will change

from LOW

to HIGH

May change

from HIGH

to LOW

Will change

from HIGH

to LOW

Don’t Care:

Changes

Allowed

Changing:

State Not

Known

N/A Center Line

is High

Impedance

SLAVE

ADDRESS

BYTE

ADDRESS

SLAVE

ADDRESS

DATA

SDA BUS

SIGNALS

FROM THE

SLAVE

SIGNALS

FROM THE

MASTER

010011011111111111001101

FIGURE 10. CONTROL REGISTER READ SEQUENCE

X4003, X4005

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P16

X4005S8IZ-2.7A

Mfr. #:

Buy X4005S8IZ-2.7A

Manufacturer:

Renesas / Intersil

Description:

Supervisory Circuits CPU SUP/WDT I2CS HI 6V IND 2 93VTRIP

Lifecycle:

New from this manufacturer.

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X4005S8IZ-2.7A

X4005S8IZ-2.7A

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