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74HC258DB,112

P1-P3P4-P6P7-P9P10-P12P13-P14
74HC258_4 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 04 — 14 April 2008 7 of 14
NXP Semiconductors
74HC258
Quad 2-input multiplexer; 3-state; inverting
11. Waveforms
Measurement points are given in Table 8.
V
OL
and V
OH
are typical output voltage levels that occur with the output load.
Fig 6. Input (nI0, nI1 and S) to output (nY) propagation delays and output transition times
001aab970
S, nI0, nI1
input
nY output
V
M
V
OH
V
I
GND
V
OL
t
PHL
t
THL
t
TLH
t
PLH
V
M
Measurement points are given in Table 8.
V
OL
and V
OH
are typical output voltage levels that occur with the output load.
Fig 7. Enable and disable times
V
M
OE input
output
LOW to OFF
OFF to LOW
output
HIGH to OFF
OFF to HIGH
V
M
001aab971
t
f
t
r
t
PLZ
V
M
t
PZL
t
PHZ
t
PZH
V
X
V
Y
outputs
enabled
outputs
disabled
outputs
enabled
V
OH
V
I
GND
GND
V
OL
V
CC
Table 8. Measurement points
Input Output
V
M
V
M
V
X
V
Y
0.5 × V
CC
0.5 × V
CC
0.1 × V
CC
0.9 × V
CC
74HC258_4 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 04 — 14 April 2008 8 of 14
NXP Semiconductors
74HC258
Quad 2-input multiplexer; 3-state; inverting
Test data is given in Table 9.
Definitions test circuit:
R
T
= Termination resistance should be equal to output impedance Z
o
of the pulse generator.
C
L
= Load capacitance including jig and probe capacitance.
R
L
= Load resistance.
S1 = Test selection switch.
Fig 8. Test circuit for measuring switching times
V
M
V
M
t
W
t
W
10 %
90 %
0 V
V
I
V
I
negative
pulse
positive
pulse
0 V
V
M
V
M
90 %
10 %
t
f
t
r
t
r
t
f
001aad983
DUT
V
CC
V
CC
V
I
V
O
R
T
R
L
S1
C
L
open
G
Table 9. Test data
Supply voltage Input Load S1
V
CC
V
I
t
r
= t
f
C
L
R
L
t
PZL
, t
PLZ
t
PZH
, t
PHZ
t
PHL
, t
PLH
2.0 V V
CC
6 ns 50 pF 1 kΩ V
CC
GND open
4.5 V V
CC
6 ns 50 pF 1 kΩ V
CC
GND open
6.0 V V
CC
6 ns 50 pF 1 kΩ V
CC
GND open
5.0 V V
CC
6 ns 15 pF 1 kΩ V
CC
GND open
74HC258_4 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 04 — 14 April 2008 9 of 14
NXP Semiconductors
74HC258
Quad 2-input multiplexer; 3-state; inverting
12. Package outline
Fig 9. Package outline SOT38-4 (DIP16)
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC JEDEC JEITA
SOT38-4
95-01-14
03-02-13
M
H
c
(e )
1
M
E
A
L
seating plane
A
1
w M
b
1
b
2
e
D
A
2
Z
16
1
9
8
E
pin 1 index
b
0 5 10 mm
scale
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
UNIT
A
max.
12
b
1
(1) (1)
(1)
b
2
cD E e M
Z
H
L
mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
min.
A
max.
b
max.
w
M
E
e
1
1.73
1.30
0.53
0.38
0.36
0.23
19.50
18.55
6.48
6.20
3.60
3.05
0.2542.54 7.62
8.25
7.80
10.0
8.3
0.764.2 0.51 3.2
inches
0.068
0.051
0.021
0.015
0.014
0.009
1.25
0.85
0.049
0.033
0.77
0.73
0.26
0.24
0.14
0.12
0.010.1 0.3
0.32
0.31
0.39
0.33
0.030.17 0.02 0.13
DIP16: plastic dual in-line package; 16 leads (300 mil)
SOT38-4
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74HC258DB,112

Mfr. #:
Buy 74HC258DB,112
Manufacturer:
NXP Semiconductors
Description:
IC QUAD 2-IN MUX 3ST INV 16-SSOP
Lifecycle:
New from this manufacturer.
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