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AT49F002T-90PI

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
AT49F002(N)(T)
7
AC Read Waveforms
(1)(2)(3)(4)
Notes: 1. CE may be delayed up to t
ACC
- t
CE
after the address transition without impact on t
ACC
.
2. OE may be delayed up to t
CE
- t
OE
after the falling edge of CE without impact on t
CE
or by t
ACC
- t
OE
after an address change
without impact on t
ACC
.
3. t
DF
is specified from OE or CE whichever occurs first (CL = 5 pF).
4. This parameter is characterized and is not 100% tested.
Input Test Waveform and
Measurement Level
t
R
, t
F
< 5 ns
Output Load Test
Note: 1. This parameter is characterized and is not 100% tested.
AC Read Characteristics
Symbol Parameter
AT49F002(N)(T)
Units
-55-70-90-12
Min Max Min Max Min Max Min Max
t
ACC
Address to Output Delay 55 70 90 120 ns
t
CE
(1)
CE to Output Delay 55 70 90 120 ns
t
OE
(2)
OE to Output Delay 0 30 0 35 0 40 0 50 ns
t
DF
(3)(4)
CE or OE to Output Float 0 25 0 25 0 25 0 30 ns
t
OH
Output Hold from OE, CE
or Address, whichever
occurred first
0000ns
ADDRESS
OUTPUT
HIGH Z
OUTPUT
OE
CE
t
ACC
t
OE
t
DF
t
OH
t
CE
VALID
ADDRESS VALID
5.0V
1.8K
100 pF
30 pF
1.3K
5.0V
1.8K
OUTPUT
PIN
1.3K
OUTPUT
PIN
50 ns
70/90/120 ns
Pin Capacitance
f = 1 MHz, T = 25°C
(1)
Symbol Typ Max Units Conditions
C
IN
46pFV
IN
= 0V
C
OUT
812pFV
OUT
= 0V
AT49F002(N)(T)
8
AC Byte Load Waveforms
WE Controlled
CE Controlled
AC Byte Load Characteristics
Symbol Parameter Min Max Units
t
AS
, t
OES
Address, OE Set-up Time 0 ns
t
AH
Address Hold Time 50 ns
t
CS
Chip Select Set-up Time 0 ns
t
CH
Chip Select Hold Time 0 ns
t
WP
Write Pulse Width (WE or CE)90ns
t
DS
Data Set-up Time 50 ns
t
DH
, t
OEH
Data, OE Hold Time 0 ns
t
WPH
Write Pulse Width High 90 ns
t
DH
t
DS
t
AS
t
AH
t
WP
CE
ADDRESS
DATA IN
OE
t
OES
t
OEH
WE
t
CS
t
CH
t
WPH
t
DH
t
DS
t
AS
t
AH
t
WP
WE
ADDRESS
DATA IN
OE
t
OES
t
OEH
CE
t
CS
t
CH
t
WPH
AT49F002(N)(T)
9
Program Cycle Waveforms
Sector or Chip Erase Cycle Waveforms
Notes: 1. OE must be high only when WE and CE are both low.
2. For chip erase, the address should be 5555. For sector erase, the address depends on what sector is to be erased.
(See note 4 under command definitions.)
3. For chip erase, the data should be 10H, and for sector erase, the data should be 30H.
Program Cycle Characteristics
Symbol Parameter Min Typ Max Units
t
BP
Byte Programming Time 10 50 µs
t
AS
Address Set-up Time 0 ns
t
AH
Address Hold Time 50 ns
t
DS
Data Set-up Time 50 ns
t
DH
Data Hold Time 0 ns
t
WP
Write Pulse Width 90 ns
t
WPH
Write Pulse Width High 90 ns
t
EC
Erase Cycle Time 10 seconds
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

AT49F002T-90PI

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Buy AT49F002T-90PI
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Description:
IC FLASH 2M PARALLEL 32DIP
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