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74HC107N,652

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19
74HC_HCT107 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4 — 26 January 2015 10 of 19
NXP Semiconductors
74HC107; 74HCT107
Dual JK flip-flop with reset; negative-edge trigger
Measurement points are given in Table 8.
V
OL
and V
OH
are typical voltage output levels that occur with the output load.
Fig 6. Reset propagation delays, pulse width and recovery time
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9
,
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9
,
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Table 8. Measurement points
Type Input Output
V
I
V
M
V
M
74HC107 V
CC
0.5V
CC
0.5V
CC
74HCT107 3 V 1.3 V 1.3 V
74HC_HCT107 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4 — 26 January 2015 11 of 19
NXP Semiconductors
74HC107; 74HCT107
Dual JK flip-flop with reset; negative-edge trigger
Test data is given in Table 9.
Definitions test circuit:
R
T
= Termination resistance should be equal to output impedance Z
o
of the pulse generator.
C
L
= Load capacitance including jig and probe capacitance.
R
L
= Load resistance.
S1 = Test selection switch.
Fig 7. Test circuit for measuring switching times
Table 9. Test data
Type Input Load S1 position
V
I
t
r
, t
f
C
L
R
L
t
PHL
, t
PLH
t
PZH
, t
PHZ
t
PZL
, t
PLZ
74HC107 V
CC
6ns 15pF, 50 pF 1k open GND V
CC
74HCT107 3 V 6 ns 15 pF, 50 pF 1 k open GND V
CC
74HC_HCT107 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4 — 26 January 2015 12 of 19
NXP Semiconductors
74HC107; 74HCT107
Dual JK flip-flop with reset; negative-edge trigger
12. Package outline
Fig 8. Package outline SOT27-1 (DIP14)
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P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19

74HC107N,652

Mfr. #:
Buy 74HC107N,652
Manufacturer:
NXP Semiconductors
Description:
Flip Flops DUAL J-K W/NEG-EDGE TRIG
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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