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74HC107N,652

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19
74HC_HCT107 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4 — 26 January 2015 7 of 19
NXP Semiconductors
74HC107; 74HCT107
Dual JK flip-flop with reset; negative-edge trigger
10. Dynamic characteristics
Table 7. Dynamic characteristics
GND (ground = 0 V); C
L
= 50 pF unless otherwise specified; for test circuit, see Figure 7
Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit
Min Typ Max Min Max Min Max
74HC107
t
pd
propagation
delay
nCP to nQ; see Figure 5
[1]
V
CC
= 2.0 V - 52 160 - 200 - 240 ns
V
CC
= 4.5 V - 19 32 - 40 - 48 ns
V
CC
=5.0V; C
L
=15pF - 16 - - - - - ns
V
CC
= 6.0 V - 15 27 - 34 - 41 ns
nCP
to nQ; see Figure 5
V
CC
= 2.0 V - 52 160 - 200 - 240 ns
V
CC
= 4.5 V - 19 32 - 40 - 48 ns
V
CC
=5.0V; C
L
=15pF - 16 - - - - - ns
V
CC
= 6.0 V - 15 27 - 34 - 41 ns
nR
to nQ, nQ; see Figure 6
V
CC
= 2.0 V - 52 155 - 195 - 235 ns
V
CC
= 4.5 V - 19 31 - 39 - 47 ns
V
CC
=5.0V; C
L
=15pF - 16 - - - - - ns
V
CC
= 6.0 V - 15 26 - 33 - 40 ns
t
t
transition time nQ, nQ; see Figure 5
[2]
V
CC
= 2.0 V - 19 75 - 95 - 110 ns
V
CC
= 4.5 V - 7 15 - 19 - 22 ns
V
CC
= 6.0 V - 6 13 - 16 - 19 ns
t
W
pulse width nCP input, HIGH or LOW;
see Figure 5
V
CC
= 2.0 V 80 22 - 100 - 120 - ns
V
CC
= 4.5 V 16 8 - 20 - 24 - ns
V
CC
= 6.0 V 14 6 - 17 - 20 - ns
nR
input, HIGH or LOW;
see Figure 6
V
CC
= 2.0 V 80 22 - 100 - 120 - ns
V
CC
= 4.5 V 16 8 - 20 - 24 - ns
V
CC
= 6.0 V 14 6 - 17 - 20 - ns
t
rec
recovery time nR to nCP; see Figure 6
V
CC
= 2.0 V 60 19 - 75 - 90 - ns
V
CC
= 4.5 V 12 7 - 15 - 18 - ns
V
CC
= 6.0 V 20 6 - 13 - 15 - ns
t
su
set-up time nJ, nK to nCP; see Figure 5
V
CC
= 2.0 V 100 22 - 125 - 150 - ns
V
CC
= 4.5 V 20 8 - 25 - 30 - ns
V
CC
= 6.0 V 17 6 - 21 - 26 - ns
74HC_HCT107 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4 — 26 January 2015 8 of 19
NXP Semiconductors
74HC107; 74HCT107
Dual JK flip-flop with reset; negative-edge trigger
t
h
hold time nJ, nK to nCP; see Figure 5
V
CC
= 2.0 V 3 6- 3 - 3 - ns
V
CC
= 4.5 V 3 2- 3 - 3 - ns
V
CC
= 6.0 V 3 2- 3 - 3 - ns
f
max
maximum
frequency
nCP input; see Figure 5
V
CC
= 2.0 V 6 23 - 4.8 - 4.0 - MHz
V
CC
= 4.5 V 30 70 - 24 - 20 - MHz
V
CC
=5.0V; C
L
=15pF - 78 - - - - - MHz
V
CC
= 6.0 V 35 85 - 28 - 24 - MHz
C
PD
power
dissipation
capacitance
per flip-flop;
V
I
=GNDtoV
CC
[3]
-30- - - - - pF
74HCT107
t
pd
propagation
delay
nCP to nQ; see Figure 5
[1]
V
CC
= 4.5 V - 19 36 - 45 - 54 ns
V
CC
=5.0V; C
L
=15pF - 16 - - - - - ns
nCP
to nQ; see Figure 5
V
CC
= 4.5 V - 21 36 - 45 - 54 ns
V
CC
=5.0V; C
L
=15pF - 18 - - - - - ns
nR
to nQ, nQ; see Figure 6
V
CC
= 4.5 V - 20 38 - 48 - 57 ns
V
CC
=5.0V; C
L
=15pF - 17 - - - - - ns
t
t
transition time nQ, nQ; see Figure 5
[2]
V
CC
= 4.5 V - 7 15 - 19 - 22 ns
t
W
pulse width nCP input, HIGH or LOW;
see Figure 5
V
CC
= 4.5 V 16 9 - 20 - 24 - ns
nR
input, HIGH or LOW;
see Figure 6
V
CC
= 4.5 V 20 11 - 25 - 30 - ns
t
rec
recovery time nR to nCP; see Figure 6
V
CC
= 4.5 V 14 8 - 18 - 21 - ns
t
su
set-up time nJ, nK to nCP; see Figure 5
V
CC
= 4.5 V 20 7 - 25 - 30 - ns
t
h
hold time nJ, nK to nCP; see Figure 5
V
CC
= 4.5 V 5 2- 5 - 5 - ns
Table 7. Dynamic characteristics
…continued
GND (ground = 0 V); C
L
= 50 pF unless otherwise specified; for test circuit, see Figure 7
Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit
Min Typ Max Min Max Min Max
74HC_HCT107 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4 — 26 January 2015 9 of 19
NXP Semiconductors
74HC107; 74HCT107
Dual JK flip-flop with reset; negative-edge trigger
[1] t
pd
is the same as t
PHL
, t
PLH
.
[2] t
t
is the same as t
THL
, t
TLH
.
[3] C
PD
is used to determine the dynamic power dissipation (P
D
in W).
P
D
=C
PD
V
CC
2
f
i
N+(C
L
V
CC
2
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in V;
N = number of inputs switching;
(C
L
V
CC
2
f
o
) = sum of outputs.
11. Waveforms
f
max
maximum
frequency
nCP input; see Figure 5
V
CC
= 4.5 V 30 66 - 24 - 20 - MHz
V
CC
=5.0V; C
L
=15pF - 73 - - - - - MHz
C
PD
power
dissipation
capacitance
per flip-flop;
V
I
=GNDtoV
CC
1.5 V
[3]
-30- - - - - pF
Table 7. Dynamic characteristics
…continued
GND (ground = 0 V); C
L
= 50 pF unless otherwise specified; for test circuit, see Figure 7
Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit
Min Typ Max Min Max Min Max
The shaded areas indicate when the input is permitted to change for predictable output performance.
Measurement points are given in Table 8
.
V
OL
and V
OH
are typical voltage output levels that occur with the output load.
Fig 5. Clock propagation delays, pulse width, set-up and hold times, output transition times and the maximum
frequency
W
VX
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:
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9
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,
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9
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9
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2/
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Q4RXWSXW
W
3+/
W
3/+
9
0
W
7/+
W
7+/
W
7/+
9
0
W
7+/
W
3/+
W
3+/
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19

74HC107N,652

Mfr. #:
Buy 74HC107N,652
Manufacturer:
NXP Semiconductors
Description:
Flip Flops DUAL J-K W/NEG-EDGE TRIG
Lifecycle:
New from this manufacturer.
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