XRA1404
10
8-BIT SPI GPIO EXPANDER WITH INTEGRATED LEVEL SHIFTERS REV. 1.0.0
Test 3: All inputs are steady at VCC or GND to minimize standby current. If internal pull-up is enabled, input voltage level
should be the same as VCC. SCL and SI are at GND. CS# is at VCC. All GPIOs are configured as inputs. Outputs are left
floating or in tri-state mode.
AC ELECTRICAL CHARACTERISTICS - SPI-BUS TIMING SPECIFICATIONS
Unless otherwise noted: TA=-40
o
to +85
o
C, Vcc=1.65V - 3.6V
SYMBOL PARAMETER
LIMITS
±
MIN MAX
LIMITS
±
MIN MAX
LIMITS
±
MIN MAX
UNIT CONDITIONS
f
SCL
Operating frequency 15 26 26 MHz
T
CSS
CS# to SCL setup time 20 20 20 ns
T
CSH
CS# to SCL hold time 20 20 20 ns
T
DO
SCL fall to SO valid time 100 100 100 ns C
L
= 30 pF
T
DS
SI to SCL setup time 20 20 20 ns
T
DH
SI to SCL hold time 20 20 20 ns
T
CP
SCL period 66 38 38 ns T
CH
+ T
CL
T
CH
SCL HIGH time 30 15 15 ns
T
CL
SCL LOW time 30 15 15 ns
T
CSW
CS# HIGH pulse width 30 30 30 ns
T
D13
SPI input pin interrupt clear 200 200 200 ns
NOTE: The Vcc comes from the VCC pin.
1.8V 10% 2.5V 10% 3.3V 10%
