6
LT1610
APPLICATIONS INFORMATION
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OPERATION
The LT1610 combines a current mode, fixed frequency
PWM architecture with Burst Mode micropower operation
to maintain high efficiency at light loads. Operation can be
best understood by referring to the block diagram in
Figure 2. Q1 and Q2 form a bandgap reference core whose
loop is closed around the output of the converter. When
V
IN
is 1V, the feedback voltage of 1.23V, along with an
70mV drop across R5 and R6, forward biases Q1 and Q2’s
base collector junctions to 300mV. Because this is not
enough to saturate either transistor, FB can be at a higher
voltage than V
IN
. When there is no load, FB rises slightly
above 1.23V, causing V
C
(the error amplifier’s output) to
decrease. When V
C
reaches the bias voltage on hysteretic
comparator A1, A1’s output goes low, turning off all
circuitry except the input stage, error amplifier and low-
battery detector. Total current consumption in this state is
30µA. As output loading causes the FB voltage to de-
crease, A1’s output goes high, enabling the rest of the IC.
Switch current is limited to approximately 100mA initially
after A1’s output goes high. If the load is light, the output
voltage (and FB voltage) will increase until A1’s output
goes low, turning off the rest of the LT1610. Low fre-
quency ripple voltage appears at the output. The ripple
frequency is dependent on load current and output capaci-
tance. This Burst Mode operation keeps the output regu-
lated and reduces average current into the IC, resulting in
high efficiency even at load currents of 1mA or less.
If the output load increases sufficiently, A1’s output remains
high, resulting in continuous operation. When the LT1610
is running continuously, peak switch current is controlled
by V
C
to regulate the output voltage. The switch is turned
on at the beginning of each switch cycle. When the sum-
mation of a signal representing switch current and a ramp
generator (introduced to avoid subharmonic oscillations at
duty factors greater than 50%) exceeds the V
C
signal,
comparator A2 changes state, resetting the flip-flop and
turning off the switch. Output voltage increases as switch
current is increased. The output, attenuated by a resistor
divider, appears at the FB pin, closing the overall loop.
Frequency compensation is provided by either an external
series RC network connected between the V
C
pin and
ground or the internal RC network on the COMP pin (Pin
8). The typical values for the internal RC are 50k and 50pF.
LAYOUT
Although the LT1610 is a relatively low current device, its
high switching speed mandates careful attention to layout
for optimum performance. For boost converters, follow
the component placement indicated in Figure 3 for the best
results. C2’s negative terminal should be placed close to
Pin 4 of the LT1610. Doing this reduces switching currents
in the ground copper which keeps high frequency “spike”
noise to a minimum. Tie the local ground into the system
ground plane at one point only, using a few vias, to avoid
introducing dI/dt induced noise into the ground plane.
1
2
8
7
3
4
6
5
L1
C2
LT1610
V
OUT
V
IN
GND
SHUTDOWN
R1
R2
MULTIPLE
VIAs
GROUND PLANE
1610 F03
+
C1
D1
+
Figure 3. Recommended Component Placement for Boost Converter. Note Direct High Current Paths Using
Wide PC Traces. Minimize Trace Area at Pin 1 (V
C
) and Pin 2 (FB). Use Multiple Vias to Tie Pin 4 Copper to
Ground Plane. Use Vias at One Location Only to Avoid Introducing Switching Currents into the Ground Plane
