ZL30123GGG2 Datasheet ZL30123GGG2, ZL30123GGG | P7-P9

ZL30123 Data Sheet

Zarlink Semiconductor Inc.

J10 p1_clk0 O Programmable Synthesizer 1 - Output Clock 0 (LVCMOS). This output can be

configured to provide any frequency with a multiple of 8 kHz up to 77.76 MHz in

addition to 2 kHz. The default frequency for this output is 1.544 MHz (DS1).

K10 p1_clk1 O Programmable Synthesizer1 - Output Clock 1 (LVCMOS). This is a

programmable clock output configurable as a multiple or division of the p1_clk0

frequency within the range of 2 kHz to 77.76 MHz. The default frequency for this

output is 3.088 MHz (2x DS1).

H10 fb_clk O Feedback Clock (LVCMOS). This output is a buffered copy of the feedback

clock for DPLL1. The frequency of this output always equals the frequency of the

selected reference.

E1 dpll2_ref O DPLL2 Selected Output Reference (LVCMOS). This is a buffered copy of the

output of the reference selector for DPLL2. Switching between input reference

clocks at this output is not hitless.

B10

diff0_p

diff0_n

O Differential Output Clock 0 (LVPECL). This output can be configured to provide

any one of the available SDH clocks. The default frequency for this clock output

is 155.52 MHz.

A10

diff1_p

diff1_n

O Differential Output Clock 1 (LVPECL). This output can be configured to provide

any one of the available SDH clocks. The default frequency for this clock output

is 622.08 MHz clock.

Control

H5 rst_b I Reset (LVCMOS, Schmitt Trigger). A logic low at this input resets the device. To

ensure proper operation, the device must be reset after power-up. Reset should

be asserted for a minimum of 300 ns.

J5 dpll1_hs_en I

DPLL1 Hitless Switching Enable (LVCMOS, Schmitt Trigger). A logic high at

this input enables hitless reference switching. A logic low disables hitless

reference switching and re-aligns DPLL1’s output phase to the phase of the

selected reference input. This feature can also be controlled through software

registers. This pin is internally pull up to Vdd.

dpll1_mod_sel0

dpll1_mod_sel1

DPLL1 Mode Select 1:0 (LVCMOS, Schmitt Trigger). During reset, the levels

on these pins determine the default mode of operation for DPLL1 (Automatic,

Normal, Holdover or Freerun). After reset, the mode of operation can be

controlled directly with these pins, or by accessing the dpll1_modesel register

through the serial interface. This pin is internally pull up to Vdd.

K1 diff0_en I

Differential Output 0 Enable (LVCMOS, Schmitt Trigger). When set high, the

differential LVPECL output 0 driver is enabled. When set low, the differential

driver is tristated reducing power consumption. This pin is internally pull up to

Vdd.

D3 diff1_en I

Differential Output 1 Enable (LVCMOS, Schmitt Trigger). When set high, the

differential LVPECL output 1 driver is enabled. When set low, the differential

driver is tristated reducing power consumption.This pin is internally pull up to

Vdd.

Pin # Name

I/O

Type

Description

ZL30123 Data Sheet

Zarlink Semiconductor Inc.

Status

H1 dpll1_lock O Lock Indicator (LVCMOS). This is the lock indicator pin for DPLL1. This output

goes high when DPLL1’s output is frequency and phase locked to the input

reference.

J1 dpll1_holdover O Holdover Indicator (LVCMOS). This pin goes high when DPLL1 enters the

holdover mode.

Serial Interface

E2 sck I Clock for Serial Interface (LVCMOS). Serial interface clock.

F1 si I Serial Interface Input (LVCMOS). Serial interface data input pin.

G1 so O Serial Interface Output (LVCMOS). Serial interface data output pin.

E3 cs_b I

Chip Select for Serial Interface (LVCMOS). Serial interface chip select. This

pin is internally pull up to Vdd.

G2 int_b O Interrupt Pin (LVCMOS). Indicates a change of device status prompting the

processor to read the enabled interrupt service registers (ISR). This pin is an

open drain, active low and requires an external pull up to VDD.

APLL Loop Filter

A6 sdh_filter A External Analog PLL Loop Filter terminal.

B6 filter_ref0 A Analog PLL External Loop Filter Reference.

C6 filter_ref1 A Analog PLL External Loop Filter Reference.

JTAG and Test

J4 tdo O Test Serial Data Out (Output). JTAG serial data is output on this pin on the

falling edge of tck. This pin is held in high impedance state when JTAG scan is

not enabled.

K2 tdi I

Test Serial Data In (Input). JTAG serial test instructions and data are shifted in

on this pin. This pin is internally pull up to Vdd. If this pin is not used then it

should be left unconnected.

H4 trst_b I

Test Reset (LVCMOS). Asynchronously initializes the JTAG TAP controller by

putting it in the Test-Logic-Reset state. This pin should be pulsed low on power-

up to ensure that the device is in the normal functional state. This pin is internally

pulled up to Vdd. If this pin is not used then it should be connected to GND.

K3 tck I Test Clock (LVCMOS): Provides the clock to the JTAG test logic. If this pin is not

used then it should be pulled down to GND.

J3 tms I

Test Mode Select (LVCMOS). JTAG signal that controls the state transitions of

the TAP controller. This pin is internally pulled up to V

. If this pin is not used

then it should be left unconnected.

Pin # Name

I/O

Type

Description

ZL30123 Data Sheet

Zarlink Semiconductor Inc.

Master Clock

K4 osci I Oscillator Master Clock Input (LVCMOS). This input accepts a 20 MHz

reference from a clock oscillator (TCXO, OCXO). The stability and accuracy of

the clock at this input determines the free-run accuracy and the long term

holdover stability of the output clocks.

K5 osco O Oscillator Master Clock Output (LVCMOS). This pin must be left unconnected

when the osci pin is connected to a clock oscillator.

Miscellaneous

B5 NC No Connection. Leave unconnected.

C5 IC No Connection. Leave unconnected.

D1 IC No Connection. Leave unconnected.

J2 IC Internal Connection. Connect to ground.

J6 IC Internal Connection. Connect to ground.

G3 IC No Connection. Leave unconnected.

K6 IC Internal Connection. Leave unconnected.

F2 IC Internal Connection. Leave unconnected.

F3 IC Internal Connection. Leave unconnected.

H7 IC Internal Connection. Connect to ground.

Power and Ground

Positive Supply Voltage. +3.3V

nominal.

CORE

Positive Supply Voltage. +1.8V

nominal.

C10

Positive Analog Supply Voltage. +3.3V

nominal.

CORE

Positive Analog Supply Voltage. +1.8V

nominal.

Pin # Name

I/O

Type

Description

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27

ZL30123GGG2

Mfr. #:

Buy ZL30123GGG2

Manufacturer:

Microchip / Microsemi

Description:

Clock Generators & Support Products Pb Free SONET/SDH PLL Line Card Synch.

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New from this manufacturer.

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ZL30123GGG2

ZL30123GGG2

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