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ZL30123GGG

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27
ZL30123 Data Sheet
16
Zarlink Semiconductor Inc.
The feedback clock (fb_clk) of DPLL1 is available as an output clock. Its output frequency is always equal to
DPLL1’s selected input frequency.
The output clocks and frame pulses derived from the SONET/SDH APLL are always synchronous with DPLL1, and
the clocks and frame pulses generated from the programmable synthesizers can be synchronized to either DPLL1
or DPLL2. This allows the ZL30123 to have two independent timing paths.
Figure 6 - Output Clock Configuration
The supported frequencies for the output clocks and frame pulses are shown in Table 4.
diff0_p/n,
diff1_p/n
(LVPECL)
sdh_clk0,
sdh_clk1
(LVCMOS)
p0_clk0, p1_clk0
(LVCMOS)
p0_clk1, p1_clk1
(LVCMOS)
sdh_fp0, shd_fp1,
p0_fp0, p0_fp1
(LVCMOS)
6.48 MHz 6.48 MHz 2 kHz p
x
_clk0
p
x
_clk1 =
2
M
166.67 Hz
(48x 125 μs frames)
19.44 MHz 9.72 MHz N * 8 kHz (up to
77.76 MHz)
400 Hz
38.88 MHz 12.96 MHz 1 kHz
51.84 MHz 19.44 MHz 2 kHz
77.76 MHz 25.92 MHz 4 kHz
155.52 MHz 38.88 MHz 8 kHz
311.04 MHz 51.84 MHz 32 kHz
622.08 MHz 77.76 MHz 64 kHz
Table 4 - Output Clock and Frame Pulse Frequencies
DPLL2
p0_clk0
p0_fp0
p0_clk1
p0_fp1
P0
Synthesizer
DPLL1
p1_clk0
p1_clk1
P1
Synthesizer
sdh_clk0
sdh_fp0
sdh_clk1
sdh_fp1
SONET/SDH
APLL
diff0
diff1
Feedback
Synthesizer
fb_clk
ZL30123 Data Sheet
17
Zarlink Semiconductor Inc.
1.6 Configurable Input-to-Output and Output-to-Output Delays
The ZL30123 allows programmable static delay compensation for controlling input-to-output and output-to-output
delays of its clocks and frame pulses.
All of the output synthesizers (SONET/SDH, P0, P1, Feedback) locked to DPLL1 can be configured to lead or lag
the selected input reference clock using the DPLL1 Fine Delay. The delay is programmed in steps of 119.2 ps with
a range of -128 to +127 steps giving a total delay adjustment in the range of -15.26 ns to +15.14 ns. Negative
values delay the output clock, positive values advance the output clock. Synthesizers that are locked to DPLL2 are
unaffected by this delay adjustment.
In addition to the fine delay introduced in the DPLL1 path, the SONET/SDH, P0, and P1 synthesizers have the
ability to add their own fine delay adjustments using the P0 Fine Delay, P1 Fine Delay, and SDH Fine Delay.
These delays are also programmable in steps of 119.2 ps with a range of -128 to +127 steps.
In addition to these delays, the single-ended output clocks of the SONET/SDH, P0, and P1 synthesizers can be
independently offset by 90, 180 and 270 degrees using the Coarse Delay, and the SONET/SDH differential outputs
can be independently delayed by -1.6 ns, 0 ns, +1.6 ns or +3.2 ns using the Diff Delay. The output frame pulses
(SONET/SDH, P0) can be independently offset with respect to each other using the FP Delay.
Figure 7 - Phase Delay Adjustments
DPLL1
DPLL2
P0 Fine Delay
p0_clk0
p0_clk1
p0_fp0
p0_fp1
P0
Synthesizer
Coarse Delay
Coarse Delay
FP Delay
FP Delay
fb_clk
p1_clk0
p1_clk1
P1 Fine Delay
Diff Delay
Diff Delay
diff0
diff1
SONET/SDH
APLL
sdh_clk0
sdh_clk1
sdh_fp0
sdh_fp1
SDH Fine Delay
Feedback
Synthesizer
DPLL1 Fine Delay
Coarse Delay
Coarse Delay
FP Delay
FP Delay
Coarse Delay
Coarse Delay
P1
Synthesizer
ZL30123 Data Sheet
18
Zarlink Semiconductor Inc.
2.0 Software Configuration
The ZL30123 is mainly controlled by accessing software registers through the serial peripheral interface (SPI). The
device can be configured to operate in a highly automated manner which minimizes its interaction with the system’s
processor, or it can operate in a manual mode where the system processor controls most of the operation of the
device.
The following table provides a summary of the registers available for status updates and configuration of the device.
.
Addr
(Hex)
Register
Name
Reset
Value
(Hex)
Description Type
Miscellaneous Registers
00 id_reg A7 Chip and version identification and reset ready
indication register
R
01 use_hw_ctrl 00 Allows some functions of the device to be
controlled by hardware pins
R/W
Interrupts
02 ref_fail_isr FF Reference failure interrupt service register R
03 dpll1_isr 70 DPLL1 interrupt service register StickR
04 dpll2_isr 00 DPLL2 interrupt service register StickR
05 ref_mon_fail_0 FF Ref0 and ref1 failure indications StickR
06 ref_mon_fail_1 FF Ref2 and ref3 failure indications. StickR
07 ref_mon_fail_2 FF Ref4 and ref5 failure indications StickR
08 ref_mon_fail_3 FF Ref6 and ref7 failure indications StickR
09 ref_fail_isr_mask 00 Reference failure interrupt service register
mask
R/W
0A dpll1_isr_mask 00 DPLL1 interrupt service register mask R/W
0B dpll2_isr_mask 00 DPLL2 interrupt service register mask R/W
0C ref_mon_fail_mask_0 FF Control register to mask each failure indicator
for ref0 and ref1
R/W
0D ref_mon_fail_mask_1 FF Control register to mask each failure indicator
for ref2 and ref3
R/W
0E ref_mon_fail_mask_2 FF Control register to mask each failure indicator
for ref4 and ref5
R/W
0F ref_mon_fail_mask_3 FF Control register to mask each failure indicator
for ref6 and ref7
R/W
Reference Monitor Setup
10 detected_ref_0 FF Ref0 and ref1 auto-detected frequency value
status register
R
11 detected_ref_1 FF Ref2 and ref3 auto-detected frequency value
status register
R
Table 5 - Register Map
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27

ZL30123GGG

Mfr. #:
Buy ZL30123GGG
Manufacturer:
Microchip / Microsemi
Description:
IC SONET/SDH SYNCH 100CABGA
Lifecycle:
New from this manufacturer.
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