ZL30123 Data Sheet
23
Zarlink Semiconductor Inc.
5E sdh_fp1_offset_1 00 Bits [15:8] of the programmable frame pulse
phase offset in multiples of 1/311.04 MHz
R/W
5F sdh_fp1_offset_2 00 Bits [21:16] of the programmable frame pulse
phase offset in multiples of 8 kHz cycles
R/W
Differential Output Configuration
60 diff_ctrl A3 Control register to enable diff0, diff1 and
diffout1_high
R/W
61 diff_sel 53 Control register to select the diff0 and diff1
frequencies
R/W
External Feedback Configuration
62 fb_control 81 Control register to enable fb_clk and the FB
PLL, int/ext feedback select
R/W
63 fb_offset_fine F5 Control register for the output/output phase
alignment fine tuning
R/W
64 reserved
Custom Input Frequencies
65 ref_freq_mode_0 00 Control register to set whether to use auto
detect, CustomA or CustomB for ref0 to ref3
R/W
66 ref_freq_mode_1 00 Control register to set whether to use auto
detect, CustomA or CustomB for ref4 to ref7
R/W
67 custA_mult_0 00 Control register for the [7:0] bits of the custom
configuration A. This is the N integer for the
N*8kHz reference monitoring.
R/W
68 custA_mult_1 00 Control register for the [13:8] bits of the custom
configuration A. This is the N integer for the
N*8kHz reference monitoring.
R/W
69 custA_scm_low 00 Control register for the custom configuration A:
single cycle SCM low limiter
R/W
6A custA_scm_high 00 Control register for the custom configuration
A: single cycle SCM high limiter
R/W
6B custA_cfm_low_0 00 Control register for the custom configuration
A: The [7:0] bits of the single cycle CFM low
limit
R/W
6C custA_cfm_low_1 00 Control register for the custom configuration
A: The [15:0] bits of the single cycle CFM low
limit
R/W
6D custA_cfm_hi_0 00 Control register for the custom configuration
A: The [7:0] bits of the single cycle CFM high
limit
R/W
Addr
(Hex)
Register
Name
Reset
Value
(Hex)
Description Type
Table 5 - Register Map (continued)
