13
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6881.1
August 28, 2012
part, connect it to the adjacent net (LGATE2/PHASE2) can
reduce trace inductance.
• Shorten all gate drive loops (UGATE-PHASE and
LGATE-PGND) and route them closely spaced.
• Minimize the inductance of the PHASE node. Ideally, the
source of the upper and the drain of the lower MOSFET
should be as close as thermally allowable.
• Minimize the current loop of the output and input power
trains. Short the source connection of the lower MOSFET
to ground as close to the transistor pin as feasible. Input
capacitors (especially ceramic decoupling) should be
placed as close to the drain of upper and source of lower
MOSFETs as possible.
• Avoid routing relatively high impedance nodes (such as
PWM and ENABLE lines) close to high dV/dt UGATE and
PHASE nodes.
In addition, connecting the thermal pad of the QFN package
to the power ground through multiple vias, or placing a low
noise copper plane (such as power ground) underneath the
SOIC part is recommended. This is to improve heat
dissipation and allow the part to achieve its full thermal
potential.
Upper MOSFET Self Turn-On Effects At Start-up
Should the driver have insufficient bias voltage applied, its
outputs are floating. If the input bus is energized at a high
dV/dt rate while the driver outputs are floating, due to the
self-coupling via the internal C
GD
of the MOSFET, the
UGATE could momentarily rise up to a level greater than the
threshold voltage of the MOSFET. This could potentially turn
on the upper switch and result in damaging in-rush energy.
Therefore, if such a situation (when input bus powered up
before the bias of the controller and driver is ready) could
conceivably be encountered, it is common practice to place
a resistor (R
UGPH
) across the gate and source of the upper
MOSFET to suppress the Miller coupling effect. The value of
the resistor depends mainly on the input voltage’s rate of
rise, the C
GD
/C
GS
ratio, as well as the gate-source
threshold of the upper MOSFET. A higher dV/dt, a lower
C
DS
/C
GS
ratio, and a lower gate-source threshold upper
FET will require a smaller resistor to diminish the effect of
the internal capacitive coupling. For most applications, the
integrated 20kΩ typically sufficient, not affecting normal
performance and efficiency.
The coupling effect can be roughly estimated with the
equations in Equation 7, which assume a fixed linear input
ramp and neglect the clamping effect of the body diode of
the upper drive and the bootstrap capacitor. Other parasitic
components such as lead inductances and PCB
capacitances are also not taken into account. These
equations are provided for guidance purposes only. Thus,
the actual coupling effect should be examined using a very
high impedance (10MΩ or greater) probe to ensure a safe
design margin.
V
GS_MILLER
dV
dt
-------
RC
rss
1e
V–
DS
dV
dt
-------
RC⋅
iss
⋅
----------------------------------
–
⎝⎠
⎜⎟
⎜⎟
⎜⎟
⎜⎟
⎛⎞
⋅⋅=
RR
UGPH
R
GI
+=
C
rss
C
GD
=
C
iss
C
GD
C
GS
+=
(EQ. 7)
FIGURE 9. GATE TO SOURCE RESISTOR TO REDUCE
UPPER MOSFET MILLER COUPLING
VIN
Q
UPPER
D
S
G
R
GI
R
UGPH
BOOT
DU
C
DS
C
GS
C
GD
DL
PHASE
VCC
ISL6611A
C
BOOT
UGATE
ISL6611A
