10 DS734F5
5.4 Power Supply Characteristics
5.4 Power Supply Characteristics
(Measurements performed under operating conditions)
5.5 Thermal Data (48-pin LQFP)
Parameter Symbol Min Typ Max Unit
High-level input voltage V
IH
2.0 V
Low-level input voltage, except XTI V
IL
——0.8V
Low-level input voltage, XTI V
ILXTI
——0.6V
Input hysteresis V
hys
—0.4— V
High-level output voltage (I
O
= –2 mA), except XTI V
OH
VDDIO*0.9 V
Low-level output voltage (I
O
= 2 mA), except XTI V
OL
——VDDIO*0.1V
Input leakage XTI I
LXTI
—— 5 µA
Input leakage current (all digital pins with internal pull-up resistors enabled) I
LEAK
——7A
Parameter Min Typ Max Unit
Operational Power Supply Current:
VDD: Core and I/O operating
1
1.Dependent on application firmware and DSP clock speed.
203 mA
VDDA: PLL operating —8 mA
VDDIO: With most ports operating —27 mA
Total Operational Power Dissipation: 480 mW
Standby Power Supply Current:
VDD: Core and I/O not clocked 100 µA
VDDA: PLL halted —1 µA
VDDIO: All connected I/O pins 3-stated by other ICs in system 50 µA
Total Standby Power Dissipation 348 µW
Parameter Symbol Min Typ Max Unit
Junction Temperature T
j
——125 °C
Thermal Resistance (Junction to Ambient)
Two-layer board
1
Four-layer board
2
1.Two-layer board is specified as a 76 mm X 114 mm, 1.6 mm thick FR-4 material with 1 oz. copper covering 20% of the top and bottom layers.
2.Four-layer board is specified as a 76 mm X 114 mm, 1.6 mm thick FR-4 material with 1 oz. copper covering 20% of the top and bottom layers and 0.5
oz. copper covering 90 % of the internal power plane and ground plane layers.
θ
ja
63.5 °C/Watt
—54
Thermal Resistance (Junction to Top of Package)
Two-layer board
3
Four-layer board
4
3.To calculate the die temperature for a given power dissipation
T
j
= Ambient Temperature + [(Power Dissipation in Watts)*θ
ja
]
4.To calculate the case temperature for a given power dissipation
T
c
= T
j
– [(Power Dissipation in Watts)*ψ
jt
]
ψ
jt
0.70 °C/Watt
—0.64
11 DS734F5
5.6 Switching Characteristics—RESET
5.6 Switching Characteristics—RESET
Figure 5-1. RESET Timing
5.7 Switching Characteristics—XTI
Figure 5-2. XTI Timing
5.8 Switching Characteristics—Internal Clock
Parameter Symbol Min Max Unit
RESET# minimum pulse width low T
rstl
1—ms
All bidirectional pins high-Z after RESET# low T
rst2z
100 ns
Configuration pins setup before RESET# high T
rstsu
50 ns
Configuration pins hold after RESET# high T
rsthld
20 ns
Parameter Symbol Min Max Unit
External Crystal operating frequency
1
1.Part characterized with the following crystal frequency values: 11.2896, 12.288, 18.432, 24.576, & 27 MH.z
F
xtal
11.2896 27 MHz
XTI period T
clki
33.3 100 ns
XTI high time T
clkih
13.3 ns
XTI low time T
clkil
13.3 ns
External Crystal Load Capacitance (parallel resonant)
2
2.C
L
refers to the total load capacitance as specified by the crystal manufacturer. Crystals that require a C
L
outside this range should be avoided. The
crystal oscillator circuit design should follow the crystal manufacturers recommendation for load capacitor selection.
C
L
10 18 pF
External Crystal Equivalent Series Resistance ESR 50
Ω
Parameter Symbol Min Max Unit
Internal DCLK frequency
1
F
dclk
——MHz
CS4852x-CQZ
CS4854x-CQZ
CS4856x-CQZ
CS4854x-DQZ
CS4856x-DQZ
F
xtal
F
xtal
F
xtal
F
xtal
F
xtal
150
150
150
150
150
RESET#
T
rst2z
T
rstl
T
rstsu
T
rsthld
HS[3:0]
All Bidirectional
Pins
t
clkih
t
clkil
T
clki
XTI
12 DS734F5
5.9 Switching Characteristics—Serial Control Port–SPI Slave Mode
5.9 Switching Characteristics—Serial Control Port–SPI Slave Mode
Figure 5-3. Serial Control Port–SPI Slave Mode Timing
Internal DCLK period
1
DCLKP ns
CS4852x-CQZ
CS4854x-CQZ
CS4856x-CQZ
CS4854x-DQZ
CS4856x-DQZ
6.7
6.7
6.7
6.7
6.7
1/F
xtal
1/F
xtal
1/F
xtal
1/F
xtal
1/F
xtal
1.After initial power-on reset, F
dclk
= F
xtal
. After initial kick-start commands, the PLL is locked to max F
dclk
and remains locked until the next power-on
reset.
Parameter Symbol Min Typical Max Units
SCP_CLK frequency
1
1.The specification f
spisck
indicates the maximum speed of the hardware. The system designer should be aware that the actual maximum speed of the
communication port may be limited by the firmware application. Flow control using the SCP_BSY# pin should be implemented to prevent overflow of
the input data buffer. At boot the maximum speed is F
xtal
/3.
f
spisck
——25MHz
SCP_CS# falling to SCP_CLK rising t
spicss
24 ns
SCP_CLK low time t
spickl
20 ns
SCP_CLK high time t
spickh
20 ns
Setup time SCP_MOSI input t
spidsu
5—ns
Hold time SCP_MOSI input t
spidh
5—ns
SCP_CLK low to SCP_MISO output valid t
spidov
——11ns
SCP_CLK falling to SCP_IRQ# rising t
spiirqh
20 ns
SCP_CS# rising to SCP_IRQ# falling t
spiirql
0—ns
SCP_CLK low to SCP_CS# rising t
spicsh
24 ns
SCP_CS# rising to SCP_MISO output high-Z t
spicsdz
—20ns
SCP_CLK rising to SCP_BSY# falling t
spicbsyl
—3*DCLKP+20 ns
Parameter Symbol Min Max Unit
SCP_BSY#
SCP_CS#
SCP_CLK
SCP_MOSI
SCP_MISO
SCP_IRQ#
0
12670
56
7
t
spicss
t
spickl
t
spickh
t
spidsu
t
spidh
t
spidov
A6 A5 A0 R/W MSB LSB
MSB
LSB
t
spicsh
t
spibsyl
t
spiirql
t
spiirqh
f
spisck
t
spicsdz

CS48560-DQZR

Mfr. #:
Manufacturer:
Cirrus Logic
Description:
Audio DSPs IC HghPrfrmnc 32-bit Audio Decoder DSP
Lifecycle:
New from this manufacturer.
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