DS1996
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HARDWARE CONFIGURATION Figure 8
TRANSACTION SEQUENCE
The protocol for accessing the DS1996 via the 1-Wire port is as follows:
Initialization
ROM Function Command
Memory Function Command
Transaction/Data
INITIALIZATION
All transactions on the 1-Wire bus begin with an initialization sequence. The initialization sequence
consists of a reset pulse transmitted by the bus master followed by presence pulse(s) transmitted by the
slave(s).
The presence pulse lets the bus master know that the DS1996 is on the bus and is ready to operate. For
more details, see the ”1-Wire Signaling” section.
ROM FUNCTION COMMANDS
Once the bus master has detected a presence, it can issue one of the six ROM function commands. All
ROM function commands are 8 bits long. A list of these commands follows (refer to flowchart in Figure
9).
Read ROM [33H]
This command allows the bus master to read the DS1996’s 8-bit family code, unique 48-bit serial
number, and 8-bit CRC. This command can only be used if there is a single DS1996 on the bus. If more
than one slave is present on the bus, a data collision will occur when all slaves try to transmit at the same
time (open drain will produce a wired-AND result). The resultant family code and 48-bit serial number
will usually result in a mismatch of the CRC.
R
x
= RECEIVE
T
x
= TRANSMIT
DS1996
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Match ROM [55H]
The match ROM command, followed by a 64-bit ROM sequence, allows the bus master to address a
specific DS1996 on a multidrop bus. Only the DS1996 that exactly matches the 64-bit ROM sequence
will respond to the subsequent memory function command. All slaves that do not match the 64-bit ROM
sequence will wait for a reset pulse. This command can be used with a single or multiple devices on the
bus.
Skip ROM [CCH]
This command can save time in a single drop bus system by allowing the bus master to access the
memory functions without providing the 64-bit ROM code. If more than one slave is present on the bus
and a read command is issued following the Skip ROM command, data collision will occur on the bus as
multiple slaves transmit simultaneously (open drain pulldowns will produce a wiredAND result).
Search ROM [F0H]
When a system is initially brought up, the bus master might not know the number of devices on the 1-
Wire bus or their 64-bit ROM codes. The search ROM command allows the bus master to use a process
of elimination to identify the 64-bit ROM codes of all slave devices on the bus. The search ROM process
is the repetition of a simple 3-step routine: read a bit, read the complement of the bit, then write the
desired value of that bit. The bus master performs this simple, 3-step routine on each bit of the ROM.
After one complete pass, the bus master knows the contents of the ROM in one device. The remaining
number of devices and their ROM codes may be identified by additional passes. See Chapter 5 of the
Book of DS19xx iButton Standards for a comprehensive discussion of a search ROM, including an actual
example.
Overdrive Skip ROM [3CH]
On a single-drop bus this command can save time by allowing the bus master to access the memory
functions without providing the 64-bit ROM code. Unlike the normal Skip ROM command the Overdrive
Skip ROM sets the DS1996 in the Overdrive Mode (OD=1). All communication following this command
has to occur at Overdrive Speed until a reset pulse of minimum 480 µs duration resets all devices on the
bus to regular speed (OD=0).
When issued on a multidrop bus this command will set all Overdrive-capable devices into Overdrive
mode. To subsequently address a specific Overdrive-capable device, a reset pulse at Overdrive speed has
to be issued followed by a Match ROM or Search ROM command sequence. This will shorten the time
for the search process. If more than one slave supporting Overdrive is present on the bus and the
Overdrive Skip ROM command is followed by a read command, data collision will occur on the bus as
multiple slaves transmit simultaneously (open drain pulldowns will produce a wired-AND result).
Overdrive Match ROM [69H]
The Overdrive Match ROM command, followed by a 64-bit ROM sequence transmitted at Overdrive
Speed, allows the bus master to address a specific DS1996 on a multidrop bus and to simultaneously set it
in Overdrive Mode. Only the DS1996 that exactly matches the 64-bit ROM sequence will respond to the
subsequent memory function command. Slaves already in Overdrive mode from a previous Overdrive
Skip or Match command will remain in Overdrive mode. All other slaves that do not match the 64-bit
ROM sequence or do not support Overdrive will return to or remain at regular speed and wait for a reset
pulse of minimum 480 µs duration. The Overdrive Match ROM command can be used with a single or
multiple devices on the bus.
DS1996
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1-WIRE SIGNALING
The DS1996 requires strict protocols to ensure data integrity. The protocol consists of four types of
signaling on one line: Reset Sequence with Reset Pulse and Presence Pulse, Write 0, Write 1 and Read
Data. All these signals except presence pulse are initiated by the bus master. The DS1996 can
communicate at two different speeds, regular speed and Overdrive speed. If not explicitly set into the
overdrive mode, the DS1996 will communicate at regular speed. While in Overdrive Mode the fast timing
applies to all wave forms.
The initialization sequence required to begin any communication with the DS1996 is shown in Figure 10.
A reset pulse followed by a presence pulse indicates the DS1996 is ready to send or receive data given the
correct ROM command and memory function command. The bus master transmits (TX) a reset pulse
(t
RSTL
, minimum 480 µs at regular speed, 48 µs at Overdrive speed). The bus master then releases the line
and goes into receive mode (RX). The 1-Wire bus is pulled to a high state via the pullup resistor. After
detecting the rising edge on the data contact, the DS1996 waits (t
PDH
, 15-60 µs at regular speed, 2-6 µs at
Overdrive speed) and then transmits the presence pulse (t
PDL
, 60-240 µs at regular speed, 8-24 µs at
Overdrive speed).
A Reset Pulse of 480 µs or longer will exit the Overdrive Mode returning the device to regular speed. If
the DS1996 is in Overdrive Mode and the Reset Pulse is no longer than 80 µs the device will remain in
Overdrive Mode.

DS1996L-F5+

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Manufacturer:
Maxim Integrated
Description:
iButtons & Accessories 64Kb Memory iButton
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