DS1996
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INITIALIZATION PROCEDURE “RESET AND PRESENCE PULSES” Figure 10
Regular Speed Overdrive Speed
480 µs ≤ t
RSTL
< ∞ * 48 µs ≤ t
RSTL
< 80 µs
480 µs ≤ t
RSTH
< ∞ (includes recovery time) 48 µs ≤ t
RSTH
< ∞
15 µs ≤
PDH
< 60 µs 2 µs ≤ t
PDH
< 6 µs
60 µs ≤ t
PDL
< 240 µs 7 µs ≤ t
PDL
< 24 µs
* In order not to mask interrupt signaling by other devices on the 1-Wire bus, t
RSTL
+ t
R
should always be
less than 960 µs.
READ/WRITE TIME SLOTS
The definitions of write and read time slots are illustrated in Figure 11. All time slots are initiated by the
master driving the data line low. The falling edge of the data line synchronizes the DS1996 to the master
by triggering a delay circuit in the DS1996. During write time slots, the delay circuit determines when the
DS1996 will sample the data line. For a read data time slot, if a ”0” is to be transmitted, the delay circuit
determines how long the DS1996 will hold the data line low overriding the 1 generated by the master. If
the data bit is a ”1”, the iButton will leave the read data time slot unchanged.
READ/WRITE TIMING DIAGRAM Figure 11
Write-One Time Slot
Regular Speed Overdrive Speed
60 µs ≤ t
SLOT
< 120 µs 6 µs ≤ t
SLOT
< 16 µs
1 µs ≤ t
LOW1
< 15 µs 1 µs ≤ t
LOW1
< 2 µs
1 µs ≤ t
REC
< ∞ 1 µs ≤ t
REC
< ∞
MASTER
DS1996
MASTER
