LTC2965
10
2965fb
For more information www.linear.com/LTC2965
applicaTions inForMaTion
Error Analysis
V
IN
thresholds are subject to the following errors:
• REF Voltage Variation (V
REF
)
• Comparator Offset (V
OS
)
• Internal Divider Range Error (A
VERR
)
• External Resistive Divider Error (A
XERR
)
The effect these errors have on the V
IN
threshold is
expressed by:
V
ERR
=RANGE ±V
OS
±V
REF
V
INH(L)
V
REF
±V
INH(L)
A
XERR
±RANGE A
VERR
V
INH(L)
A
XERR
=2
TOLERANCE
100
1–
V
INH(L)
V
REF
External divider error is determined by the percentage toler-
ance values of the resistors. If 1% tolerance resistors are
used in
the external divider then there is a 2% worst-case
voltage error associated with it. The effects of comparator
offset and V
REF
voltage are uncorrelated with each other.
Therefore, a Root-Sum-Square can be applied to the error
voltage referred to V
IN
. Using the example from Threshold
Configuration and assuming 1% resistors implement the
external resistive divider, the falling V
IN
threshold of ap-
proximately 18V has an error tolerance of:
V
ERR(REF)
= RANGE
( )
±∆V
REF
V
INL
V
REF
= 10
( )
±24mV
1.8V
2.402V
=±180mV
V
ERR(EXT)
= RANGE
( )
±V
INL
2 0.01 1–
V
INL
V
REF
= 10
( )
±1.8V 0.005
( )
=±90mV
V
ERR(VOS)
= RANGE
( )
±∆V
OS
( )
= 10
( )
±16mV
( )
=±160mV
V
ERR(RS)
= RANGE
( )
±A
VERR
( )
±V
INL
( )
= 10
( )
±0.004
( )
1.8V
( )
=±72mV
V
ERR
= V
ERR(REF)
2
+V
ERR(EXT)
2
+V
ERR(VOS)
2
+V
ERR(RS)
2
= ±180mV
( )
2
+ ±90mV
( )
2
+ ±160mV
( )
2
+ ±72mV
( )
2
=±267mV
The actual V
IN
falling threshold has an error tolerance of
±267mV or ±1.48%.
Improving Threshold Accuracy
The biggest threshold error terms are:
• External Resistive Divider Accuracy
• REF Voltage Variation
Even using 1% tolerance resistors, external resistive divider
accuracy still accounts for as much as ±2% threshold error
while REF voltage variation accounts for ±1% threshold
error. In order to minimize these threshold error terms,
an external reference can be used to set the thresholds for
INH/INL as shown in Figure 4. An LT6656-2.048 has an
initial accuracy of 0.05% and provides bias via the 0.1%
resistive divider network for INH and INL. It is biased off
of the LTC2965 REF pin. The threshold error tolerance
is calculated using the method described in the Typical
Applications section with V
REF
= ±1.024mV given the
initial accuracy of the LT6656 2.048V output and using
0.1% tolerance resistors for the external divider.
V
ERR(REF)
= RANGE
( )
±∆V
REF
V
INL
V
REF
= 10
( )
±1.024mV
1.8V
2.048V
=±9mV
V
ERR(EXT)
= RANGE
( )
±V
INL
2 0.001 1–
V
INL
V
REF
= 10
( )
±1.8V 0.0005
( )
=±9mV
V
ERR(VOS)
= RANGE
( )
±∆V
OS
( )
= 10
( )
±1.6mV
( )
=±16mV
V
ERR(RS)
= RANGE
( )
±A
VERR
( )
±V
INL
( )
= 10
( )
±0.004
( )
1.8V
( )
=±72mV
V
ERR
= V
ERR(REF)
2
+V
ERR(EXT)
2
+V
ERR(VOS)
2
+V
ERR(RS)
2
= ±9mV
( )
2
+ ±9mV
( )
2
+ ±16mV
( )
2
+ ±72mV
( )
2
=±75mV
The resulting V
IN
threshold error is reduced to ±0.42%
from ±1.48% in the previous error analysis example.
LTC2965
11
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For more information www.linear.com/LTC2965
V
IN
V
IN
LTC2965
GND
REF
F
INH
INL
2965 F04
LT6656-2.048
OUT
R2
200k
0.1%
R1
1.8M
0.1%
R3
47.5k
0.1%
R4
10k
IN
GND
Figure 4. Reducing V
IN
Threshold Error
applicaTions inForMaTion
Output Configuration with Polarity Selection
The OUT pin may be used with a wide range of user-defined
voltages up to 100V with an external resistor. Select a
resistor compatible with desired output rise time and load
current specifications. When the status outputs are low,
power is dissipated in the pull-up resistors. An internal
pull-up is present if the OUT pins are left floating or if
low power consumption is required. The internal pull-up
resistor does not draw current if an external resistor pulls
OUT up to a voltage greater than V
OH
.
If PS is connected to ground, the comparator output is
noninverting. This means that OUT pulls low when V
IN
falls below the scaled INL voltages. OUT is released after
V
IN
rises above the scaled INH voltage. Likewise, if PS is
connected up to REF or a voltage > V
TH
, the comparator
output is inverting. This means that OUT pulls low when
V
IN
rises above the scaled INH voltage and is released
when V
IN
falls below the scaled INL voltage.
If the V
IN
pin falls below the UVLO threshold minus
hysteresis, the output is pulled to ground. The output is
guaranteed to stay low for V
IN
1.25V regardless of the
output logic configuration.
It is recommended that circuit board traces associated
with the OUT pin be located on a different layer than those
associated with the INH/INL and REF pins where possible
to avoid capacitive coupling.
Hot Swap™ Events
The LTC2965 can withstand high voltage transients up
to 140V. However, when a supply voltage is abruptly
connected to the input resonant ringing can occur as a
result of series inductance. The peak voltage could rise
to 2x the input supply, but in practice can reach 2.5x if
a capacitor with a strong voltage coefficient is present.
Circuit board trace inductances of as little as 10nH can
produce significant ringing. Ringing beyond the absolute
maximum specification can be destructive to the part and
should be avoided whenever possible. One effective means
to eliminate ringing seen at the V
IN
pins and to protect the
part is to include a 1kΩ to 5kΩ resistance between the
monitored voltage and the V
IN
pin as shown in Figure 5.
This provides damping for the resonant circuit. If there is
a decoupling capacitor on the V
IN
pins the time constant
formed by the RC network should be considered.
Figure 5. Hot Swap Protection
High Voltage Pin Creepage/Clearance Options
Appropriate spacing between component lead traces is
critical to avoid flashover between conductors. There
are multiple industry and safety standards that have
different spacing requirements depending on factors such
as operating voltage, presence of conformal coat
, elevation,
etc. The LTC2965 is available in a 16-lead MSOP package
which offers landing clearance of at least 0.79mm (0.031in).
The package incorporates unconnected pins between all
adjacent high voltage and low voltage pins to maximize
PC board trace clearance. For voltages >30V the MSOP
should be used, otherwise the smaller or DFN is sufficient
when clearance is not an issue. For more information, refer
to the printed circuit board design standards described in
IPC2221 and UL60950.
GND
LTC2965
V
INA
/V
INB
R
S
1k
V
IN
2965 F05
LTC2965
12
2965fb
For more information www.linear.com/LTC2965
Figure 6. Using Series Resistance to Dampen REF
Transient Response
Figure 7. V
REF
Load Transient
Figure 8. V
REF
Line Transient
6a 6b
6c
applicaTions inForMaTion
Voltage Reference
The REF pin is a buffered reference with a voltage of V
REF
referenced to GND. A bypass capacitor up to 1000pF
in value can be driven by the REF pin directly. Larger
capacitances require a series resistance to dampen the
transient response as shown in Figure 6A. If a resistive
divider is already present then the bypass capacitor can
be connected to the INH or INL pin as shown in Figure 6B.
Figure 6C shows the resistor value required for different
capacitor values to achieve critical damping. Bypassing the
reference can help prevent false tripping of the compara
-
tors by preventing glitches on the INH/INL pins. Figure 7
shows the reference load transient response. Figure 8
shows the reference line transient response
.
If there is a
decoupling capacitor on the INH/INL pin the time constant
formed by the RC network should be considered. Use a
capacitor with a compatible voltage rating.
GND
LTC2965
REF
INL
INH
R
S
C
REF
2965 F06ab
GND
LTC2965
REF
INL
INH
R
S
C
REF
CAPACITANCE VALUE (µF)
RESISTANCE VALUE (kΩ)
2965 F06c
100
10
1
0.1
0.001 0.1 10.01
100µs/DIV
100µA
2.4V
50mV/DIV
10µA
2965 F07
1nF
10nF + 4.3kΩ
0.1µF + 1.5kΩ
1µF + 600Ω
V
REF
LOAD CURRENT
10µs/DIV
1V/DIV
3.5V
8V
2.4V
10mV/DIV
2965 F08
1nF
1µF + 600Ω
V
REF
V
IN

LTC2965CMS#TRPBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Supervisory Circuits 100V Single Micropower Voltage Monitor
Lifecycle:
New from this manufacturer.
Delivery:
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