AD7233ANZ Datasheet AD7233ANZ, AD7233BNZ | P4-P6

AD7233

REV. B

–3–

ABSOLUTE MAXIMUM RATINGS

= 25°C unless otherwise noted)

to GND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +17 V

to GND . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –17 V

OUT

to GND . . . . . . . . . . . . . . . . . . . . –6 V to V

+0.3 V

Digital Inputs to GND . . . . . . . . . . . . –0.3 V to V

+0.3 V

Operating Temperature Range

Industrial (A, B Versions) . . . . . . . . . . . . . –40°C to +85°C

Storage Temperature Range . . . . . . . . . . . –65°C to +150°C

Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . . 300°C

Power Dissipation to 75°C . . . . . . . . . . . . . . . . . . . . 450 mW

Derates above 75°C by . . . . . . . . . . . . . . . . . . . . . 10 mW/°C

ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >4000 V

NOTES

Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the

device at these or any other conditions above those listed in the operational sections

of this specification is not implied. Exposure to absolute maximum rating condi-

tions for extended periods may affect device reliability.

The output may be shorted to voltages in this range provided the power dissipation

of the package is not exceeded. Short circuit current is typically 80 mA.

ORDERING GUIDE

Temperature Relative Package

Model Range Accuracy Option*

AD7233AN –40°C to +85°C ± 1 LSB N-8

AD7233BN –40°C to +85°C ± 1/2 LSB N-8

*N = Plastic DIP.

TERMINOLOGY

RELATIVE ACCURACY (LINEARITY)

Relative accuracy, or endpoint linearity, is a measure of the

maximum deviation of the DAC transfer function from a straight

line passing through the endpoints of the transfer function. It is

measured after allowing for zero and full-scale errors and is

expressed in LSBs or as a percentage of full-scale reading.

DIFFERENTIAL NONLINEARITY

Differential nonlinearity is the difference between the measured

change and the ideal 1 LSB change between any two adjacent

codes. A specified differential nonlinearity of ± 1 LSB or less

over the operating temperature range ensures monotonicity.

BIPOLAR ZERO ERROR

Bipolar zero error is the voltage measured at V

OUT

when the

DAC is loaded with all 0s. It is due to a combination of offset

errors in the DAC, amplifier and mismatch between the internal

gain resistors around the amplifier.

FULL-SCALE ERROR

Full-scale error is a measure of the output error when the

amplifier output is at full scale (full scale is either positive or

negative full scale).

DIGITAL-TO-ANALOG GLITCH IMPULSE

This is the voltage spike that appears at the output of the DAC

when the digital code in the DAC latch changes before the out-

put settles to its final value. The energy in the glitch is specified

in nV secs, and is measured for an all codes change (0000 0000

0000 to 1111 1111 1111).

DIGITAL FEEDTHROUGH

This is a measure of the voltage spike that appears on V

OUT

as a

result of feedthrough from the digital inputs on the AD7233. It

is measured with LDAC held high.

AD7233

REV. B

–4–

PIN FUNCTION DESCRIPTIONS

Pin Mnemonic Description

Positive Supply (12 V to 15 V).

2 SCLK Serial Clock, Logic Input. Data is clocked into the input register on each falling SCLK edge.

3 SDIN Serial Data In, Logic Input. The 16-bit serial data word is applied to this input.

4 SYNC Data Synchronization Pulse, Logic Input. Taking this input low initializes the internal logic in

readiness for a new data word.

5 LDAC Load DAC, Logic Input. Updates the DAC output. The DAC output is updated on the falling edge of

this signal, or alternatively if this line in permanently low, an automatic update mode is selected whereby

the DAC is updated on the 16th falling SCLK pulse.

6 GND Ground Pin = 0 V.

OUT

Analog Output Voltage. This is the buffered DAC output voltage (–5 V to +5 V).

Negative Supply (–12 V to –15 V).

DIGITAL INTERFACE

The AD7233 contains an input serial to parallel shift register

and a DAC latch. A simplified diagram of the input loading cir-

cuitry is shown in Figure 2. Serial data on the SDIN input is

loaded to the input register under control of SYNC and SCLK.

When a complete word is held in the shift register it may then be

loaded into the DAC latch under control of LDAC. Only the

data in the DAC latch determines the analog output on the

AD7233.

A low SYNC input provides the frame synchronization signal

which tells the AD7233 that valid serial data on the SDIN input

will be available for the next 16 falling edges of SCLK. An inter-

nal counter/decoder circuit provides a low gating signal so that

only 16 data bits are clocked into the input shift register. After

16 SCLK pulses the internal gating signal goes inactive (high)

thus locking out any further clock pulses. Therefore, either a

continuous clock or a burst clock source may be used to clock in

the data.

The SYNC input should be taken high after the complete 16-bit

word is loaded in.

Although 16 bits of data are clocked into the input register, only

the latter 12 bits get transferred into the DAC latch. The first 4

bits in the 16-bit stream are don’t cares since their value does

not affect the DAC latch data. Therefore the data format is 4

don’t cares followed by the 12-bit data word with the LSB as the

last bit in the serial stream.

CIRCUIT INFORMATION

D/A Section

The AD7233 contains a 12-bit voltage-mode D/A converter

consisting of highly stable thin-film resistors and high-speed

NMOS single-pole, double-throw switches.

Op Amp Section

The output of the voltage-mode D/A converter is buffered by a

noninverting CMOS amplifier. The buffer amplifier is capable

of developing ±5 V across a 2 kΩ load to GND.

OUT

DB11

DB10

DB9

DB1DB0

R R

INTERNAL

REFERENCE

GND

Figure 1. Simplified D/A Converter

TOP VIEW

(Not to Scale)

SCLK

SDIN

OUT

GND

LDAC

SYNC

AD7233

REV. B

–5–

There are two ways in which the DAC latch and hence the ana-

log output may be updated. The status of the LDAC input is

examined after SYNC is taken low. Depending on its status, one

of two update modes is selected.

If LDAC = 0 then the automatic update mode is selected. In

this mode the DAC latch and analog output are updated auto-

matically when the last bit in the serial data stream is clocked in.

The update thus takes place on the sixteenth falling SCLK edge.

If LDAC = 1 then the automatic update is disabled and the

DAC latch is updated by taking LDAC low any time after the

16-bit data transfer is complete. The update now occurs on the

falling edge of LDAC. This facility is useful for simultaneous

update in multi-DAC systems. Note that the LDAC input must

be taken back high again before the next data transfer is initiated.

SYNC

SCLK

SDIN

LDAC

RESET

ⴜ16

COUNTER/

DECODER

GATING

SIGNAL

AUTO-UPDATE

CIRCUITRY

GATING

SCLK

DAC LATCH (12 BITS)

INPUT SHIFT REGISTER (16 BITS)

Figure 2. Simplified Loading Structure

DB15

DON’T CARE

DB14

DON’T CARE

DB13

DON’T CARE

DB12

DON’T CARE

DB11

MSB

DB1

DB0

LSB

SYNC

SCLK

SDIN

LDAC

Figure 3. Timing Diagram

P1-P3 P4-P6 P7-P9

AD7233ANZ

Mfr. #:

Buy AD7233ANZ

Manufacturer:

Analog Devices Inc.

Description:

Digital to Analog Converters - DAC SERIAL 12-BIT IC

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AD7233ANZ

AD7233ANZ

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