93V855AGLFT

4
ICS93V855I
0783C—06/01/04
DC Electrical Characteristics
T
A
= -45 °C to +85 °C; Supply Voltage AVDD, VDD = 2.5 V +/ - 0.2V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Sup ply Volta ge V
DD Q
, A
VDD
2.3 2.5 2.7 V
Low level inpu t volta ge
V
IL
CLK_INT, CLK_INC, FB_INC,
FB_INT
0.4
V
DD
/2 - 0.18
V
High level input voltage
V
IH
CLK_INT, CLK_INC, FB_INC,
FB_INT
V
DD
/2 + 0.18
2.1 V
DC input signal voltage (note
2)
V
IN
-0.3
V
DD
+ 0.3
V
DC - CLK_INT, CLK_INC,
FB_INC, FB_INT
0.36
V
DD
+ 0.6
V
AC - CLK_INT, CLK_INC,
FB_INC, FB_INT
0.7
V
DD
+ 0.6
V
Output differential cross-
vo lta
g
e
(
note 4
)
V
OX
V
DD
/2 - 0.15 V
DD
/2 + 0.15
V
Input differential cross-
vo lta
g
e
(
note 4
)
V
IX
V
DD
/2 - 0.2 V
DD
/2 V
DD
/2 + 0.2
V
Operating free-air
temperature
T
A
-45 85 °C
Notes:
1
2
3
4
Differential inputs signal voltages specifies the differential voltage [VT-VCP] required f or switching,
where VTR is the true input level and VCP is the complementary input level.
Differential cross-point voltage is expected to track variations of VDD and is the voltage at which the
differen tial signal must be crossing.
Differential input signal
voltage (note 3)
V
ID
Unused inputs must be held high or low to prevent them from floating.
DC input signal voltage specifies the allowable DC excursion of differential input.
5
ICS93V855I
0783C—06/01/04
Switchin
g
Characteristics
T
A
= -45°C to +85°C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated)
PARAMETER SYMBOL CONDITION MIN TYP MAX UNITS
Max clock frequency
3
freq
op
33 233 MHz
Applicat ion Frequency
Ran
g
e
3
freq
App
60 170 MHz
Input clock duty cycle d
tin
40 60 %
Output clock slew rate
t
sl (o )
12v/ns
CLK stabilization T
STAB
100 µs
Low-to high level propagation
delay time
t
PLH
1
CLK_IN t o any output 5.5 ns
High-to low level propagation
delay time
t
PHL
1
CLK_IN t o any output 5.5 ns
Output enable time
t
en
PD# to any output 5 ns
Output disable time t
dis
PD# to any output 5 ns
Period jitter
t
jit (per)
-7 5 75 ps
Half -p eriod jitter
t
jit(hper)
-1 00 100 ps
Input clock slew rate t
sl ( I)
12v/ns
Cycle to Cycle Jitter
t
c
y
c
-t
c
y
c
-7 5 75 ps
Pha se error
4
t
(phase erro r)
-5 0 50 ps
Output to Output Skew
t
skew
40 60 ps
Rise Time, Fall Time
t
r
, t
f
Load = 120
φ
/16pF 650 800 950 ps
Notes:
1.
2.
3.
4. Does not include jitter.
Over the application
frequency range
Switching characteristics are guaranteed for application frequency range. The PLL
Locks over the Max Clock Frequency range, bu t the device do e not necessarily
meet other timing parameters.
Refers to transition on noninvertin
g
out
p
ut in PLL b
yp
ass mode.
While the pulse skew is almost constant over f requency, the duty cycle error
increases at higher frequencies. This is due to the formula: duty cycle=twH/tc,
were the c
y
cle
(
tc
)
decre ase s as the fre
q
uenc
y
g
oes u
p
.
6
ICS93V855I
0783C—06/01/04
GND
ICS93V855I
V
DD
V
DD
/2
V
(CLKC)
V
(CLKC)
SCOPE
C=16pF
-V
DD/2
-V
DD/2
-V
DD/2
V
DD/2
Z=60Ω
Z=60Ω
Z=50Ω
Z=50Ω
R=10Ω
R=10Ω
R=50Ω
R=60Ω
R=60Ω
R=50Ω
V
(TT)
V
(TT)
C=16pF
NOTE: V
(TT)
=
GND
t
c(n)
t
c(n+1)
t
jit(cc)
=t
c(n)
±t
c(n+1)
Figure 1. IBIS Model Output Load
Figure 2. Output Load Test Circuit
Y , FB_OUTC
X
Y , FB_OUTT
X
Parameter Measurement Information
ICS93V855I
Figure 3. Cycle-to-Cycle Jitter

93V855AGLFT

Mfr. #:
Manufacturer:
IDT
Description:
Clock Drivers & Distribution DDR CLOCK DRIVER
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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