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ISL84684IUZ-T

P1-P3P4-P6P7-P9P10-P12P13-P13
10
FN6088.5
July 31, 2007
FIGURE 16. TURN-OFF TIME vs SUPPLY VOLTAGE
FIGURE 17. TURN-ON TIME vs SUPPLY VOLTAGE
FIGURE 18. DIGITAL SWITCHING POINT vs SUPPLY VOLTAGE
FIGURE 19. FREQUENCY RESPONSE
FIGURE 20. CROSSTALK AND OFF ISOLATION
Die Characteristics
SUBSTRATE POTENTIAL (POWERED UP):
GND (QFN Paddle Connection: Tie to GND or Float)
TRANSISTOR COUNT:
114
PROCESS:
Submicron CMOS
Typical Performance Curves T
A
= +25°C, Unless Otherwise Specified (Continued)
t
OFF
(ns)
V+ (V)
1.0
1.5 2.0 2.5 3.0 3.5 4.0 4.5
0
50
100
150
200
+85°C
-40°C
+25°C
t
ON
(ns)
V+ (V)
1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
25
100
150
200
250
+85°C
-40°C
+25°C
V+ (V)
V
INH
AND V
INL
(V)
1.52.02.53.03.54.04.5
V
INH
V
INL
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
FREQUENCY (Hz)
0
-20
NORMALIZED GAIN (dB)
GAIN
PHASE
V+ = 3V
0
20
40
60
80
100
PHASE (°)
1M 10M 100M 600M
V
IN
= 0.2V
P-P
to 2V
P-P
R
L
= 50Ω
FREQUENCY (Hz)
1k 100k 1M 100M 500M10k 10M
-110
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
CROSSTALK (dB)
OFF ISOLATION (dB)
110
10
20
30
40
50
60
70
80
90
100
ISOLATION
CROSSTALK
V+ = 3.0V
ISL84684
11
FN6088.5
July 31, 2007
ISL84684
Wafer Level Chip Scale Package (WLCSP)
PIN 1 ID
A
E1
SD
BOTTOM VIEW
A
B
12
C
SE
3
4
b
e
D1
SIDE VIEW
A1
b
A2
TOP VIEW
bb
D
E
W4x3.10A
4X3 ARRAY 10 BALL WAFER LEVEL CHIP SCALE PACKAGE
SYMBOL MILLIMETERS NOTES
A 0.64 +0.05 -0.10 -
A1 0.29 ±0.02 -
A2 0.35 REF. -
b θ 0.37 ±0.03 -
bb θ 0.30 REF. -
D 1.50 ±0.05 -
D1 1.00 BASIC -
E 2.00 ±0.05 -
E1 1.50 BASIC -
e 0.50 BASIC -
SD 0.00 BASIC -
SE 0.25 BASIC -
N103
Rev. 1 10/05
NOTES:
1. Dimensions are in Millimeters.
2. Dimensioning and tolerancing conform to ASME 14.5M-1994.
3. Symbol “N” is the actual number of solder balls.
12
FN6088.5
July 31, 2007
ISL84684
Thin Dual Flat No-Lead Plastic Package (TDFN)
//
NX (b)
SECTION "C-C"
FOR ODD TERMINAL/SIDE
e
CC
5
C
L
TERMINAL TIP
(A1)
BOTTOM VIEW
A
6
AREA
INDEX
C
C
0.10
0.08
SIDE VIEW
0.10
2X
E
A
B
C0.10
D
TOP VIEW
CB
2X
6
8
AREA
INDEX
NX L
E2
E2/2
REF.
e
N
(Nd-1)Xe
(DATUM A)
(DATUM B)
5
0.10
87
D2
BAC
N-1
12
PLANE
SEATING
C
A
A3
NX b
D2/2
NX k
L1
9
L
M
L10.3x3A
10 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE
SYMBOL
MILLIMETERS
NOTESMIN NOMINAL MAX
A
0.70 0.75 0.80
-
A1
- - 0.05
-
A3
0.20 REF
-
b
0.20 0.25 0.30
5, 8
D
2.95 3.0 3.05
-
D2
2.25 2.30 2.35
7, 8
E
2.95 3.0 3.05
-
E2
1.45 1.50 1.55
7, 8
e
0.50 BSC
-
k
0.25 - -
-
L
0.25 0.30 0.35
8
N
10
2
Nd
5
3
Rev. 3 3/06
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd refers to the number of terminals on D.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensions are provided to assist with PCB Land
Pattern Design efforts, see Intersil Technical Brief TB389.
9. Compliant to JEDEC MO-229-WEED-3 except for D2
dimensions.
P1-P3P4-P6P7-P9P10-P12P13-P13

ISL84684IUZ-T

Mfr. #:
Buy ISL84684IUZ-T
Manufacturer:
Renesas / Intersil
Description:
Analog Switch ICs W/ANNEAL SWITCH DL 4OHM S 1 65V 3 6V
Lifecycle:
New from this manufacturer.
Delivery:
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