AD9750
–6–
REV. 0
DEFINITIONS OF SPECIFICATIONS
Linearity Error (Also Called Integral Nonlinearity or INL)
Linearity error is defined as the maximum deviation of the
actual analog output from the ideal output, determined by a
straight line drawn from zero to full scale.
Differential Nonlinearity (or DNL)
DNL is the measure of the variation in analog value, normalized
to full scale, associated with a 1 LSB change in digital input code.
Monotonicity
A D/A converter is monotonic if the output either increases or
remains constant as the digital input increases.
Offset Error
The deviation of the output current from the ideal of zero is
called offset error. For IOUTA, 0 mA output is expected when
the inputs are all 0s. For IOUTB, 0 mA output is expected
when all inputs are set to 1s.
Gain Error
The difference between the actual and ideal output span. The
actual span is determined by the output when all inputs are set
to 1s minus the output when all inputs are set to 0s.
Output Compliance Range
The range of allowable voltage at the output of a current-output
DAC. Operation beyond the maximum compliance limits may
cause either output stage saturation or breakdown resulting in
nonlinear performance.
Temperature Drift
Temperature drift is specified as the maximum change from the
ambient (+25°C) value to the value at either T
MIN
or T
MAX
. For
offset and gain drift, the drift is reported in ppm of full-scale
range (FSR) per degree C. For reference drift, the drift is
reported in ppm per degree C.
Power Supply Rejection
The maximum change in the full-scale output as the supplies
are varied from nominal to minimum and maximum specified
voltages.
Settling Time
The time required for the output to reach and remain within a
specified error band about its final value, measured from the
start of the output transition.
Glitch Impulse
Asymmetrical switching times in a DAC give rise to undesired
output transients that are quantified by a glitch impulse. It is
specified as the net area of the glitch in pV-s.
Spurious-Free Dynamic Range
The difference, in dB, between the rms amplitude of the output
signal and the peak spurious signal over the specified bandwidth.
Total Harmonic Distortion
THD is the ratio of the rms sum of the first six harmonic
components to the rms value of the measured input signal. It is
expressed as a percentage or in decibels (dB).
Multitone Power Ratio
The spurious-free dynamic range for an output containing mul-
tiple carrier tones of equal amplitude. It is measured as the
difference between the rms amplitude of a carrier tone to the
peak spurious signal in the region of a removed tone.
+1.20V REF
AVDD ACOM
REFLO
ICOMP
PMOS
CURRENT SOURCE
ARRAY
+5V
SEGMENTED SWITCHES
FOR DB9–DB1
LSB
SWITCH
REFIO
FS ADJ
DVDD
DCOM
CLOCK
+5V
R
SET
2kV
0.1mF
DVDD
DCOM
IOUTA
IOUTB
0.1mF
AD9750
SLEEP
50V
RETIMED
CLOCK
OUTPUT*
LATCHES
DIGITAL
DATA
TEKTRONIX
AWG-2021
W/OPTION 4
LECROY 9210
PULSE GENERATOR
CLOCK
OUTPUT
50V
20pF
50V
20pF
100V
TO HP3589A
SPECTRUM/
NETWORK
ANALYZER
50V INPUT
MINI-CIRCUITS
T1-1T
* AWG2021 CLOCK RETIMED
SUCH THAT DIGITAL DATA
TRANSITIONS ON FALLING EDGE
OF 50% DUTY CYCLE CLOCK.
150pF
Figure 2. Basic AC Characterization Test Set-Up
AD9750
–7–
REV. 0
Typical AC Characterization Curves @ +5 V Supplies
(AVDD = +5 V, DVDD = +5 V, I
OUTFS
= 20 mA, 50 Doubly Terminated Load, Differential Output, T
A
= +25C, SFDR up to Nyquist, unless otherwise noted)
f
OUT
– MHz
SFDR – dBc
90
80
40
1
10
70
60
50
25MSPS
100MSPS
65MSPS
125MSPS
Figure 3. SFDR vs. f
OUT
@ 0 dBFS
f
OUT
– MHz
SFDR – dBc
90
80
40
0
10
20 30 40 50
70
60
50
–12dBF
S
–6dBF
S
0dBF
S
Figure 6. SFDR vs. f
OUT
@ 100 MSPS
A
OUT
– dBF
S
SFDR – dBc
90
80
–25 –20
–15 –10 –5 0
70
60
50
455kHz/5MSPS
5.91/65MSPS
2.27MHz/25MHz
11.37MHz/125MSPS
Figure 9. Single-Tone SFDR vs. A
OUT
@ f
OUT
= f
CLOCK
/11
f
OUT
– MHz
SFDR – dBc
90
80
40
0
21246810
70
60
50
–6dBF
S
–12dBF
S
0dBF
S
Figure 4. SFDR vs. f
OUT
@ 25 MSPS
f
OUT
– MHz
SFDR – dBc
90
80
40
0
10 60
20 30 40 50
70
60
50
–12dBF
S
–6dBF
S
0dBF
S
Figure 7. SFDR vs. f
OUT
@125 MSPS
A
OUT
– dBc
SFDR – dBc
90
80
–25 –20
–15 –10 –5 0
70
60
50
1MHz/5MHz
13MHz/65MHz
25MHz/125MHz
5MHz/25MHz
Figure 10. Single-Tone SFDR vs.
A
OUT
@ f
OUT
= f
CLOCK
/5
f
OUT
– MHz
SFDR – dBc
90
80
40
0
530
10 15 20 25
70
60
50
–12dBF
S
–6dBF
S
0dBF
S
Figure 5. SFDR vs. f
OUT
@ 65 MSPS
f
OUT
– MHz
SFDR – dBc
90
80
40
0
2
46810
70
60
50
20mAF
S
10mAF
S
5mAF
S
12
Figure 8. SFDR vs. f
OUT
and I
OUTFS
@
25 MSPS and 0 dBFS
f
CLOCK
– MSPS
SNR – dB
70
66
50
0
10 60
20 30 40 50
62
58
54
I
OUTFS
= 20mA
I
OUTFS
= 5mA
I
OUTFS
= 10mA
Figure 11. SNR vs. f
CLOCK
and I
OUTFS
@ f
OUT
= 2 MHz and 0 dBFS
AD9750
–8–
REV. 0
CODE
0.2
0.15
–0.1
0
1000
800
ERROR – LSB
0.1
0.05
0
–0.05
200 400 600
Figure 12. Typical INL
f
OUT
– MHz
AMPLITUDE – dBm
0
–10
–40
620
8101214
–20
–30
16 184
–50
–60
–70
–80
–90
–100
22 24
f
CLOCK
= 125MSPS
f
OUT1
= 13.5MHz
f
OUT2
= 14.5MHz
AMPLITUDE = 0dBF
S
SDFR = 75dBc
Figure 15. Two-Tone SFDR
CODE
0.08
0.04
–0.12
0
1000
800
ERROR – LSB
0
–0.04
–0.08
200 400 600
Figure 13. Typical DNL
f
OUT
– MHz
–10
–20
–90
0
30
20
AMPLITUDE – dBm
–30
–40
–50
51015
–60
–70
–80
25
f
CLOCK
= 65MSPS
f
OUT1
= 6.25MHz
f
OUT2
= 6.75MHz
f
OUT3
= 7.25MHz
f
OUT4
= 7.75MHz
AMPLITUDE = 0dBF
S
SFDR = 70dBc
–100
Figure 16. Four-Tone SFDR
TEMPERATURE – 8C
SFDR – dBc
90
80
50
–40 100
–20 0 20 40
70
60
60 80–60
f
OUT
= 2.5MHz
f
OUT
= 10MHz
f
OUT
= 40MHz
Figure 14. SFDR vs. Temperature
@ 125 MSPS, 0 dBFS

AD9750ARUZRL7

Mfr. #:
Manufacturer:
Description:
Digital to Analog Converters - DAC 10-Bit 100 MSPS
Lifecycle:
New from this manufacturer.
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