8
Notes:
1. Each channel.
2. All devices are considered two-terminal devices; I
I-O
is measured between all input leads or terminals shorted together and all output
leads or terminals shorted together.
3. Measured between each input pair shorted together and all output connections for that channel shorted together.
4. Measured between adjacent input pairs shorted together for each multichannel device.
5. t
PHL
propagation delay is measured from the 50% point on the leading edge of the input pulse to the 1.5 V point on the leading edge of
the output pulse. The t
PLH
propagation delay is measured from the 50% point on the trailing edge of the input pulse to the 1.5 V point
on the trailing edge of the output pulse.
6. CM
L
is the maximum rate of rise of the common mode voltage that can be sustained with the output voltage in the logic low state
(V
O
< 0.8 V). CM
H
is the maximum rate of fall of the common mode voltage that can be sustained with the output voltage in the logic
high state (V
O
> 2.0 V).
7. This is a momentary withstand test, not an operating condition.
8. It is essential that a bypass capacitor (0.01 to 0.1 μF, ceramic) be connected from V
CC
to ground. Total lead length between both ends of
this external capacitor and the isolator connections should not exceed 20 mm.
9. No external pull up is required for a high logic state on the enable input.
10. The t
ELH
enable propagation delay is measured from the 1.5 V point on the trailing edge of the enable input pulse to the 1.5 V point on
the trailing edge of the output pulse.
11. The t
EHL
enable propagation delay is measured from the 1.5 V point on the leading edge of the enable input pulse to the 1.5 V point on
the leading edge of the output pulse.
12. Standard commercial parts receive 100% testing at 25°C (Subgroups 1 and 9). Class H and K parts receive 100% testing at 25, 125, and
-55°C (Subgroups 1 and 9, 2 and 10, 3 and 11, respectively).
13. Parameters are tested as part of device initial characterization and after design and process changes. Parameters are guaranteed to limits
speci ed for all lots not speci cally tested.
Figure 1. High Level Output Current vs. Tempera-
ture.
Figure 2. Input-Output Characteristics. Figure 3. Input Diode Forward Characteristics.
0
20
40
60
80
100
-60 -40 -20 0 20 40 60 80 100 120 140
T
A
- TEMPERATURE - °C
I
OH
- HIGH LEVEL OUTPUT CURRENT - uA
V
CC
= 3.3 V
V
O
= 3.3 V
I
F
= 250 μA
0
1
2
3
4
5
1234567
I
F
- INPUT DIODE FORWARD CURRENT - mA
V
O
- OUTPUT VOLTAGE -V
510 Ω
1 kΩ
4 kΩ
R
L
V
CC
= 3.3 V
T
A
= 25 °C
