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10
Figure 27. Rise Time of Gate Drive Waveform
(C
L
= 1 nF)
Figure 28. Fall Time of Gate Drive Waveform
(C
L
= 1 nF)
Figure 29. Supply Current vs. Supply Voltage
(Duty Cycle = 82% and Output Load = 1 nF)
Figure 30. Supply Current vs. Supply Voltage
(Duty Cycle = 48% and Output Load = 1 nF)
V
CC
, SUPPLY VOLTAGE (V)
Figure 31. Switch Frequency vs. C
T
Pin Capacitance
C
T
, PIN CAPACITANCE (pF)
0.5
I
C2
, SUPPLY CURRENT (mA)
−0.5
4
V
CC
, SUPPLY VOLTAGE (V)
0
3
3.5
SWITCHING FREQUENCY (kHz)
0
300
100
150
200
0151052520 0 151052
5
20
400 800600 12001000
50
250
I
C2
, SUPPLY CURRENT (mA)
2.5
2
1.5
1
0.5
−0.5
4
0
3
3.5
2.5
2
1.5
1
Ramp up to 24 V
Ramp down from 24 V
Ramp up to 24 V
Ramp down from 24 V
48% DUTY −CYCLE
82% DUTY CYCLE
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11
DETAILED OPERATING DESCRIPTIONS
INTRODUCTION
The NCP1212 implements a standard current mode
architecture where the switch−off time is dictated by the
peak current setpoint. This device represents an ideal
candidate where low external part−count is the key system
requirement. Additionally, the device provides extensive
value−added functions, Soft−Start, Brownout Detect, etc.,
that can be applied to low−cost AC−DC adaptor
applications. The NCP1212 incorporates all the necessary
functions normally needed in UC384X based power supply
systems: Oscillator section, PWM Latch section, Current
Sense section, Brownout Detect protection, Soft−Start and
Maximum Duty Cycle Selection. With all those functions,
this device becomes a good alternative to UC384X that can
help to improve both performance and system cost. Also, the
innovative Maximum Duty Cycle Selection feature allows
the device applied to both forward and fly−back mode
configurations. Detailed functions of individual internal
blocks are described in below and a simplified functional
block diagram is shown in Figure 2.
Oscillator Section
The oscillator frequency is programmed by the capacitor
connected to C
T
pin. The capacitor is charged by a constant
current source to 3.8 V and 2.5 V for 82% and 48%
maximum Duty Cycle condition respectively. Once the
selected voltage is reached, C
T
is then discharged by another
constant current source down to 1.0 V and this charging and
discharging action will carry on perpetually. Desirable
switching frequency can be selected by choosing proper
value of timing capacitor, C
T
. The C
T
pin waveform is
shown in Figure 32.
Figure 32. C
T
Pin Waveform for Oscillator
3.8 V
2.5 V
1.0 V
48%
48%
82%
PWM Latch Section
NCP1212 works in current mode. The power switch
current is converted to a positive voltage by inserting a
sensing resistor R
sense
between the power switch source and
the ground. The power switch peak current is compared with
the level shifted control input voltage on a cycle−by−cycle
basis. Figure 27 illustrated the internal blocks of the
function. The PWM latch is initialized by the Oscillator set
signal and is terminated by the current sense comparator
when the current exceeds the value dictated by the control
input or current limit level. The current sense Comparator
Latch configuration used ensures that only a single pulse
appears at the output during any given oscillator cycle.
Figure 33. PWM Latch Function
FB
+5 V
3 R
R
9 K
300 ns
LEB
S
Q
Q
Current
Limit
+
Output
+
Output
+
1 V
Oscillator
Reset
Set
R
F/F
DRV
CS
1
2
3
4
Rsense
PWM Control
Totem Pole Driver
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Current Sense Section
The current sense pin, CS detects the voltage drop across
a current sensing resistor, R
sense
connected in between the
power MOSFET and Ground. In most cases, a narrow spike
on the leading edge of the current waveform can be observed
and may cause the power supply to exhibit an instability
when the output is lightly loaded. The spike is due to the
power transformer inter−winding capacitance and output
rectifier recovery time which are unavoidable. NCP1212
provides a 300 ns Leading Edge Blanking block to shield off
the spike. With the Leading Edge Blanking function, the CS
pin is not sensitive to the power switch turn−on noise and
spikes, practically in most applications, no filtering network
is required.
In normal operation, voltage developed at the current
sense input is compared with the level shifted control input
voltage and an internal Current Limit Threshold, V
CS
. In
case the CS input exceeds the Current Limit Threshold,
which is 1.0 V (typ.) in NCP1212, the gate driver output will
be forced to turn off immediately.
Thus the maximum allowable peak current is given by the
following equation:
I
pk(max)
+
1V
R
sense
Soft−Start and Maximum Duty Selection
NCP1212 includes an internal Soft−Start function to
simplify designers job hence make this device easy to use.
During the startup phase, a constant current source of 8.0 mA
flows out of the SS/DMAX pin once V
CC
attains the
minimum startup voltage. The capacitor connected at
SS/DMAX pin is slowly charged up and the voltage
developed plus one diode drop, V
SST
is compared with the
saw−tooth waveform, C
T
from the internal oscillator as
shown in Figure 34. Whenever C
T
voltage is higher than
V
SST
, gate driver output will be turned off. Since V
SST
rises
slowly and it controls the output duty gradually increases as
shown in Figure 35. The minimum C
T
voltage is at 1.0 V,
hence there is no output before SS/DMAX pin attains about
0.4 V (1.0 V–1 diode drop). Soft−Start block will have no
effect to the PWM operation once V
SST
reaches 3.2 V.
Figure 34. Soft−Start Operation
S
Q
Q
+
F/F
Overload
Enable
Reset
+
3.2 V
From C
T
Vsst
+5 V
8 mA
Shutdown
SS/DMAX
NCP1212
Duty Cycle Control
C
SS
Figure 35. Output Pulse Duty Cycle Depends on the SS/DMAX Pin Voltage
V
SST
V
DRV
C
T

NCP1212PG

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
IC CTRLR PWM PROG CM OVP 8DIP
Lifecycle:
New from this manufacturer.
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