NCP1212PG Datasheet NCP1212P, NCP1212DR2, NCP1212DR2G | P16-P18

NCP1212

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APPLICATION INFORMATION AND TYPICAL WAVEFORMS

The NCP1212 is an ideal choice for next generation

isolated fix switching frequency forward mode converters

that only need few external components to complete the

system. Converting your existing application from using

UC384X controllers to NCP1212 is easy and simple. In

below is a description on how to determine external

components value for a typical application example. For the

schematic of the application, please refer to Figure 1 in this

data sheet.

Finding the external component values can be broken

down into several steps as introduced below:

1. Select the maximum Duty Cycle for forward mode

operation and calculate the Soft−Start time.

Select the system, operate in forward mode with

82% maximum Duty Cycle. Only a capacitor is

required at SS/DMAX pin and the Soft−Start time is

determined by the capacitor, C

. Its value is given

by the equation below:

I T

* V

where:

I is an 8.0 mA constant current source flow out of the

SS/DMAX pin;

is the required Soft−Start time;

is the Upper Threshold Voltage in the oscillator

block and which is effectively controlling the PWM

maximum Duty Cycle at gate driver output.

Soft−Start block will have no effect to the PWM

operation once SS/DMAX pin voltage reaches this

threshold. This threshold voltage is 2.5 V with 48%

maximum Duty Cycle;

is about 0.4 V (1.0 V minus one diode drop)

which is the Lower Voltage Threshold for the PWM

operation. There will be no PWM gate driver output

before SS/DMAX pin voltage attains this threshold.

For example, the required Soft−Start time is 50 ms,

the timing capacitor, C

can be calculated as:

8 mA 50 ms

2.5 V * 0.4 V

+ 0.182 mF

In this case, a 0.22 mF capacitor is used for this

application and the Soft−Start time is calculated as

57.75 ms. The charging waveform at SS/DMAX pin

is shown in Figure 40. From the captured waveform,

the charge time from 0 V to 4.0 V is 115.2 ms and for

the voltage charging up to 2.5 V, i.e. hitting the

Upper Threshold Voltage, the elapsed time is about

70 ms that matched with the theoretical calculation

closely.

Figure 40. SS/DMAX Pin Charging Waveform

115.2 ms

4.0 V

Overload condition is signified by current sense input

voltage hitting the Maximum Current Sense Threshold,

. To avoid false trigger that may happen during transient

load change, C

starts to discharge by an internal current

source of 20 mA, I

−I

and the overload protection will

only be issued until the voltage at SS/DMAX pin falls below

0.5 V. The discharging time, T

DIS

for 0.22 mF Soft−Start

capacitor is given by:

DIS

ref

* V

)

* I

where:

is the Soft−Start timing capacitor;

ref

is the internal reference voltage, 5.0 V typical;

is the internal diode forward voltage on between the

reference voltage and SS/DMAX pin in IC internal, is 0.6 V

typical;

is the overload threshold voltage. Refer to Figure 39

Overload Detection Block Diagram, the overload threshold

voltage is 0.5 V typical;

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−I

is the internal current source for C

discharging,

20 mA typical.

The discharging time for 0.22 mF Soft−Start capacitor is:

DIS

0.22 mF (5.0 V * 0.6 V * 0.5 V)

20 mA

+ 42.9 ms

The discharging waveform on SS/DMAX pin is shown in

Figure 41. The discharging time from 4.0 V to 0.6 V is

measured as 36 ms from Figure 41. By interpolation,

discharging time can be estimated as about 41.3 ms when

output is overload which agreed with the calculated result.

Figure 41. SS/DMAX Pin Discharging Waveform

36 ms

3.4 V

2. Determine the PWM Switching Frequency

The switching waveform is generated by the action

of charging and discharging by internal current

sources to a capacitor connected at C

, pin 4. The

relationship of the switching frequency and the value

of C

is governed by the equation below:

chg

* 1)

where:

chg

is the charging current to C

, 278 mA typical;

D is the selected Maximum Duty Cycle, 48% or

82%;

is the capacitor connected to C

pin;

is the threshold voltage for different Maximum

Duty Cycle selection, 2.5 V for 48% Maximum

Duty Cycle and 3.8 V for 82% Maximum Duty

Cycle.

The Switching Frequency against C

is shown in

Figure 31 to help the designers to determine the capacitance

for their selected switching frequency.

3. Determine the BOK Thresholds

Brownout detect thresholds are determined by a

resistors network that monitors part of the bulk

capacitor voltage at BOK pin. Equations below

illustrate the calculation of the resistors value for the

network.

Upper

) R

Lower

Bulk_H

* V

Bulk_L

)

45 mA

Lower

[1.21 V(V

Bulk_H

* V

Bulk_L

)]

(45 mA V

Bulk_H

)

Where V

Bulk_H

and V

Bulk_L

are the desired upper

and lower bulk capacitor voltage for brownout

detection.

Assume V

Bulk_H

= 212 Vdc and V

Bulk_L

= 186 Vdc,

select 3.3 kW for R

Lower

then R

Upper

can be

calculated to be 576 kW.

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Figure 42. Brownout Detect Waveforms

Channel 1: The MOSFET’s V

Switching Waveform

Channel 2: Primary Bulk Capacitor Voltage

Channel 3: BOK Pin Voltage

Experimental results for the Brownout action were shown

in Figure 42. From the captured waveforms, it can be noted

that the Brownout Input Threshold Voltage is 1.21 V and

Brownout Hysteresis Voltage is 1.36 V at BOK pin.

4. Improving Light Load and No Load Regulation for

High Power Applications

For high power applications, limited by the dynamic

range of the control circuitry, i.e. the control

feedback is limited by the swing of the optocoupler.

When V

reaches about 0.1 V at light load

conditions, it no longer has the means to further

reduce that voltage because of the saturation of the

optocoupler. At light load or no load conditions, the

primary current is very small and as the current

sensing resistor is also small for high power

applications, the current sense feedback voltage will

be much smaller than 0.1 V. Consequently, the

control will force to acquire maximum Duty Cycle

operation and the output will increase without

control.

In order to improve the poor regulation at light load,

a small circuit is added as shown in Figure 43. With

the additional circuitry, when V

falls below 0.1 V,

Q2 will drive additional offset current to CS pin and

modify the current sensing voltage, V

. For V

higher than 0.1 V at normal load operation, Q2 will

be turned off due to limited V

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