7
FN8114.2
August 25, 2008
Principles of Operation
Power-on Reset
Applying power to the X40030, X40031, X40034, X40035
activates a Power-on Reset Circuit that pulls the
RESET/RESET
pins active. This signal provides several
benefits.
It prevents the system microprocessor from starting to
operate with insufficient voltage.
It prevents the processor from operating prior to
stabilization of the oscillator.
It allows time for an FPGA to download its configuration
prior to initialization of the circuit.
It prevents communication to the EEPROM, greatly reducing
the likelihood of data corruption on power-up.
When V
CC
exceeds the device V
TRIP1
threshold value for
t
PURST
(selectable), the circuit releases the RESET (X40031,
X40035) and RESET (X40030, X40034) pin allowing the
system to begin operation.
FIGURE 1. CONNECTING A MANUAL RESET PUSH-BUTTON
Manual Reset
By connecting a push-button directly from MR to ground, the
designer adds manual system reset capability. The MR
pin is
LOW while the push-button is closed and RESET/RESET
pin remains HIGH/LOW until the push-button is released and
for t
PURST
thereafter.
Low Voltage V
CC
(V1 Monitoring)
During operation, the X40030, X40031, X40034, X40035
monitors the V
CC
level and asserts RESET/RESET if the
supply voltage falls below a preset minimum V
TRIP1
. The
RESET signal prevents the microprocessor from operating in
a power fail or brownout condition. The RESET/RESET
signal remains active until the voltage drops below 1V. It also
remains active until V
CC
returns and exceeds V
TRIP1
for
t
PURST
.
Low Voltage V2 Monitoring
The X40030 also monitors a second voltage level and
asserts V2FAIL
if the voltage falls below a preset minimum
V
TRIP2
. The V2FAIL signal is either ORed with RESET to
prevent the microprocessor from operating in a power fail or
brownout condition or used to interrupt the microprocessor
with notification of an impending power failure.
For the X40030 and X40031 the V2FAIL
signal remains
active until the V2MON drops below 1V (V2MON falling). It
also remains active until V2MON returns and exceeds
V
TRIP2
.This voltage sense circuitry monitors the power
supply connected to V2MON pin. If V
CC
= 0, V2MON can still
be monitored.
For the X40034 and X40035, the V2FAIL
signal remains
active until V
CC
drops below 1V and remains active until
V2MON returns and exceeds V
TRIP2
.This sense circuitry is
powered by V
CC
. If V
CC
= 0, V2MON cannot be monitored.
Low Voltage V3 Monitoring
The X40030, X40031, X40034, X40035 also monitors a third
voltage level and asserts V3FAIL
if the voltage falls below a
preset minimum V
TRIP3
. The V3FAIL signal is either ORed
with RESET to prevent the microprocessor from operating in
a power fail or brownout condition or used to interrupt the
microprocessor with notification of an impending power
failure. The V3FAIL
signal remains active until the V3MON
drops below 1V (V3MON falling). It also remains active until
V3MON returns and exceeds V
TRIP3
.
This voltage sense circuitry monitors the power supply
connected to V3MON pin. If V
CC
= 0, V3MON can still be
monitored.
Early Low V
CC
Detection (LOWLINE)
This CMOS output goes LOW earlier than RESET/RESET
whenever V
CC
falls below the V
TRIP1
voltage and returns
high when V
CC
exceeds the V
TRIP1
voltage. There is no
power-up delay circuitry (t
PURST
) on this pin.
FIGURE 2. TWO USES OF MULTIPLE VOLTAGE MONITORING
V
CC
MR
SYSTEM
RESET
MANUAL
RESET
X40030, X40034
RESET
6V TO 10V
V
CC
5V
V2MON
X40031-A
UNREG.
SUPPLY
V
CC
X40031-B
RESET
V2FAIL
SYSTEM
V
CC
RESET
RESET
V2FAIL
SYSTEM
RESET
NOTICE: NO EXTERNAL COMPONENTS REQUIRED TO MONITOR
THREE VOLTAGES.
1M
390k
V3MON
V3FAIL
V2MON
5V
REG
3.0V
REG
1.8V
REG
3.3V
V3FAIL
V3MON
(1.7V)
POWER
FAIL
INTERRUPT
V
CC
X40030, X40031, X40034, X40035
8
FN8114.2
August 25, 2008
FIGURE 3. V
TRIPX
SET/RESET CONDITIONS
Watchdog Timer
The Watchdog Timer circuit monitors the microprocessor
activity by monitoring the SDA and SCL pins. A standard
read or write sequence to any slave address byte restarts
the watchdog timer and prevents the WDO
signal from going
active. A minimum sequence to reset the watchdog timer
requires four microprocessor instructions namely, a Start,
Clock Low, Clock High and Stop. The state of two nonvolatile
control bits in the Status Register determine the watchdog
timer period. The microprocessor can change these
watchdog bits by writing to the X40030, X40031, X40034,
X40035 control register (also refer to page 21).
FIGURE 4. WATCHDOG RESTART
V1, V2 and V3 Threshold Program
Procedure (Optional)
The X40030 is shipped with standard V1, V2 and V3
threshold (V
TRIP1,
V
TRIP2,
V
TRIP3
) voltages. These values
will not change over normal operating and storage
conditions. However, in applications where the standard
thresholds are not exactly right, or if higher precision is
needed in the threshold value, the X40030, X40031, X40034,
X40035 trip points may be adjusted. The procedure is
described in the following and uses the application of a high
voltage control signal.
Setting a V
TRIPx
Voltage (x = 1, 2, 3)
There are two procedures used to set the threshold voltages
(V
TRIPx
), depending upon if the threshold voltage to be stored
is higher or lower than the present value. For example, if the
present V
TRIPx
is 2.9V and the new V
TRIPx
is 3.2V, the new
voltage can be stored directly into the V
TRIPx
cell. If however,
the new setting is to be lower than the present setting, then it
is necessary to “reset” the V
TRIPx
voltage before setting the
new value.
Setting a Higher V
TRIPx
Voltage (x = 1, 2, 3)
To set a V
TRIPx
threshold to a new voltage which is higher
than the present threshold, the user must apply the desired
V
TRIPx
threshold voltage to the corresponding input pin
(Vcc(V1MON), V2MON or V3MON). Then, a programming
voltage (Vp) must be applied to the WDO
pin before a START
condition is set up on SDA. Next, issue on the SDA pin the
Slave Address A0h, followed by the Byte Address 01h for
V
TRIP1
, 09h for V
TRIP2
, and 0Dh for V
TRIP3
, and a 00h Data
Byte in order to program V
TRIPx
. The STOP bit following a
valid write operation initiates the programming sequence. Pin
WDO
must then be brought LOW to complete the operation.
To check if the V
TRIPX
has been set, set VXMON to a value
slightly greater than V
TRIPX
(that was previously set). Slowly
ramp down VXMON and observe when the corresponding
outputs (LOWLINE
, V2FAIL and V3FAIL) switch. The voltage
at which this occurs is the V
TRIPX
(actual).
CASE A
If the desired V
TRIPX
is greater than the V
TRIPX
(actual), then
add the difference between V
TRIPX
(desired) – V
TRIPX
(actual) to the original V
TRIPX
desired. This is your new
V
TRIPX
that should be applied to VXMON and the whole
sequence should be repeated again (see Figure 5).
CASE B
If the V
TRIPX
(actual), is higher than the V
TRIPX
(desired),
perform the reset sequence as described in the next section.
V
CC
/V2MON/V3MON
V
TRIPX
V
P
t
WC
A0h
07 70 70
SCL
WDO
SDA
(X = 1, 2, 3)
00h
SCL
SDA
0.6µs
1.3µs
WDT RESET
START STOP
X40030, X40031, X40034, X40035
9
FN8114.2
August 25, 2008
The new V
TRIPX
voltage to be applied to VXMON will now
be: V
TRIPX
(desired) – (V
TRIPX
(actual) – V
TRIPX
(desired)).
Note: This operation does not corrupt the memory array.
Setting a Lower V
TRIPx
Voltage (x=1, 2, 3)
In order to set V
TRIPx
to a lower voltage than the present
value, then V
TRIPx
must first be “reset” according to the
procedure described in the following. Once V
TRIPx
has been
“reset”, then V
TRIPx
can be set to the desired voltage using
the procedure described in “Setting a Higher VTRIPx
Voltage (x = 1, 2, 3)” on page 8.
Resetting the V
TRIPx
Voltage
To reset a V
TRIPx
voltage, apply the programming voltage
(Vp) to the WDO
pin before a START condition is set up on
SDA. Next, issue on the SDA pin the Slave Address A0h
followed by the Byte Address 03h for V
TRIP1
, 0Bh for V
TRIP2
,
and 0Fh for V
TRIP3
, followed by 00h for the Data Byte in
order to reset V
TRIPx
. The STOP bit following a valid write
operation initiates the programming sequence. Pin WDO
must then be brought LOW to complete the operation.
After being reset, the value of V
TRIPx
becomes a nominal
value of 1.7V or lesser.
Note: This operation does not corrupt the memory array.
Set V
CC
1.5(V2MON or V3MON), when setting V
TRIP2
or
V
TRIP3
respectively.
Control Register
The Control Register provides the user a mechanism for
changing the Block Lock and Watchdog Timer settings. The
Block Lock and Watchdog Timer bits are nonvolatile and do
not change when power is removed.
The Control Register is accessed with a special preamble in
the slave byte (1011) and is located at address 1FFh. It can
only be modified by performing a byte write operation directly
to the address of the register and only one data byte is
allowed for each register write operation. Prior to writing to the
Control Register, the WEL and RWEL bits must be set using a
two step process, with the whole sequence requiring 3 steps.
See “Writing to the Control Registers” on page 11.
The user must issue a stop, after sending this byte to the
register, to initiate the nonvolatile cycle that stores WD1,
WD0, PUP1, PUP0 and BP. The X40030, X40031, X40034,
X40035 will not acknowledge any data bytes written after the
first byte is entered.
The state of the Control Register can be read at any time by
performing a random read at address 1FFh, using the
special preamble. Only one byte is read by each register
read operation. The master should supply a stop condition to
be consistent with the bus protocol.
RWEL: Register Write Enable Latch (Volatile)
The RWEL bit must be set to “1” prior to a write to the
Control Register.
FIGURE 5. SAMPLE V
TRIP
RESET CIRCUIT
76543 210
PUP1 WD1 WD0 BP 0 RWEL WEL PUP0
1
6
2
7
14
13
9
8
X40030
V
TRIP1
ADJ.
V
P
SDA
SCL
µC
ADJUST
RUN
V2FAIL
V
TRIP2
ADJ.
RESET
X40030, X40031, X40034, X40035

X40031S14IZ-B

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Supervisory Circuits TRPL SUPS LO I VT1 4 4 VT2 2 6 VT3 1 8
Lifecycle:
New from this manufacturer.
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