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IDT79R3041 INTEGRATED RISController FOR LOW COST SYSTEMS COMMERCIAL TEMPERATURE RANGE
PIN NAME I/O DESCRIPTION
O Byte Enable Strobes for 16-bit Memory Port: These active low outputs are the byte lane strobes for
accesses to 16-bit wide memory ports; they are not necessarily valid for 8- or 32-bit wide ports. If )
is asserted, then the most significant byte (either D(31:24) or D(15:8), depending on system endianness)
is going to be used in this transfer. If is asserted, the least significant byte (D(23:16) or D(7:0))
will be used.
can be held inactive (masked) during read transfers, according to the programming of the CP0
Bus Control register.
I
(1)
During , the act as Reset Configuration Mode bit inputs for two ReservedHigh options.
The output pins are designated as the unconnected Rsvd(3:2) pins in the R3051 and R3081.
O Last Datum in Mini-Burst: This active low output indicates that this is the last datum transfer in a given
transaction. It is asserted after the next to last (reads) or (writes), and is negated when
or is negated.
The output pin is designated in the R3051 and R3081 as the Diag(0) output pin.
O Terminal Count: This is an active low output from the processor which indicates that the on-chip timer
has reached its terminal count. It will remain low for either 1.5 clock cycles, or until software resets the
timer, depending on the mode selected in the CP0 Bus Control register. Thus, the on-chip timer can
function either as a free running timer for system functions such as DRAM refresh, or can operate as a
software controlled time-slice timer, or real-time clock.
The output pin is designated in the R3051 as the BrCond(1) input pin, and in the R3081 as the Run
pin output.
I Bus Error: Input to the bus interface unit to terminate a bus transaction due to an external bus error.
This signal is only sampled during read and write operations. If the bus transaction is a read operation,
then the CPU will take a bus error exception.
I Processor Interrupt: During normal operation, these signals are logically the same as the (5:0)
signals of the R3000A. During processor reset, these signals perform mode initialization of the CPU, but
in a different (simpler) fashion than the interrupt signals on the original R3000A.
I
(1)
During , and act as Reset Configuration Mode bit inputs for the
and BigEndian options.
There are two types of interrupt inputs: the inputs are internally synchronized by the processor,
and may be driven by an asynchronous external agent. The direct interrupt inputs are not internally
synchronized, and thus must be externally synchronized to the CPU. The direct interrupt inputs have
one cycle lower latency than the synchronized interrupts.
ClkIn I Master Clock Input: This is a double frequency input used to control the timing of the CPU.
I Master Processor Reset: This signal initializes the CPU. Reset initialization mode selection is
performed during the last cycle of .
I Tri-State: This input to the R3041 requests that the R3041 tri-state all of its outputs. In addition to those
outputs tri-stated during DMA, tri-state will cause , , and to tri-state. This signal is
intended for use during board testing and emulation during debug and board manufacture.
The input pin is designated as the unconnected Rsvd(4)pin in the R3051 and R3081.
Vcc I Power: These inputs must be supplied with the rated supply voltage (VCC). All Vcc inputs must be
connected to insure proper operation.
Vss I Ground: These inputs must be connected to ground (GND). All Vss inputs must be connected to insure
proper operation.
PIN DESCRIPTION (Continued):
2905 tbl 05
NOTE:
1. Reset Configuration Mode bit input when is asserted, normal signal
function when is de-asserted.
