AD7730LBRZ Datasheet AD7730BRUZ, AD7730BNZ, AD7730BRZ | P1-P3

REV.

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AD7730/AD7730L

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700 World Wide Web Site: http://www.analog.com

Fax: © Analog Devices, Inc.,

Bridge Transducer ADC

FUNCTIONAL BLOCK DIAGRAM

KEY FEATURES

Resolution of 230,000 Counts (Peak-to-Peak)

Offset Drift: 5 nV/C

Gain Drift: 2 ppm/C

Line Frequency Rejection: >150 dB

Buffered Differential Inputs

Programmable Filter Cutoffs

Specified for Drift Over Time

Operates with Reference Voltages of 1 V to 5 V

ADDITIONAL FEATURES

Two-Channel Programmable Gain Front End

On-Chip DAC for Offset/TARE Removal

FAST

Step™ Mode

AC or DC Excitation

Single Supply Operation

APPLICATIONS

Weigh Scales

Pressure Measurement

GENERAL DESCRIPTION

The AD7730 is a complete analog front end for weigh-scale and

pressure measurement applications. The device accepts low-

level signals directly from a transducer and outputs a serial

digital word. The input signal is applied to a proprietary pro-

grammable gain front end based around an analog modulator.

FASTStep is a trademark of Analog Devices, Inc.

SIGMA-

DELTA

MODULATOR

AD7730

6-BIT

DAC

SERIAL INTERFACE

AND CONTROL LOGIC

CLOCK

GENERATION

PROGRAMMABLE

DIGITAL

FILTER

SIGMA-DELTA A/D CONVERTER

BUFFER

PGA

100nA

AGND

100nA

VBIAS

AIN1(+)

AIN1(–)

AIN2(+)/D1

AIN2(–)/D0

ACX

STANDBY

SYNC

MCLK IN

MCLK OUT

SCLK

DIN

DOUT

RESET

RDY

POL

DGNDAGND

REF IN(–)

REF IN(+)

MUX

REFERENCE DETECT

EXCITATION

CLOCK

CALIBRATION

MICROCONTROLLER

+/–

The modulator output is processed by a low pass programmable

digital filter, allowing adjustment of filter cutoff, output rate and

settling time.

The part features two buffered differential programmable gain

analog inputs as well as a differential reference input. The part

operates from a single +5 V supply. It accepts four unipolar

analog input ranges: 0 mV to +10 mV, +20 mV, +40 mV and

+80 mV and four bipolar ranges: ± 10 mV, ± 20 mV, ± 40 mV

and ± 80 mV. The peak-to-peak resolution achievable directly

from the part is 1 in 230,000 counts. An on-chip 6-bit DAC

allows the removal of TARE voltages. Clock signals for synchro-

nizing ac excitation of the bridge are also provided.

The serial interface on the part can be configured for three-wire

operation and is compatible with microcontrollers and digital

signal processors. The AD7730 contains self-calibration and

system calibration options, and features an offset drift of less

than 5 nV/°C and a gain drift of less than 2 ppm/°C.

The AD7730 is available in a 24-pin plastic DIP, a 24-lead

SOIC and 24-lead TSSOP package. The AD7730L is available

in a 24-lead SOIC and 24-lead TSSOP package.

NOTE

The description of the functions and operation given in this data

sheet apply to both the AD7730 and AD7730L. Specifications

and performance parameters differ for the parts. Specifications

for the AD7730L are outlined in Appendix A.

2012

781/461-3113

–2–

Parameter B Version

Units Conditions/Comments

STATIC PERFORMANCE (CHP = 1)

No Missing Codes

24 Bits min

Output Noise and Update Rates

See Tables I & II

Integral Nonlinearity 18 ppm of FSR max

Offset Error

See Note 3 Offset Error and Offset Drift Refer to Both

Offset Drift vs. Temperature

5 nV/°C typ Unipolar Offset and Bipolar Zero Errors

Offset Drift vs. Time

25 nV/1000 Hours typ

Positive Full-Scale Error

2, 5

See Note 3

Positive Full-Scale Drift vs Temp

2, 6, 7

2 ppm of FS/°C max

Positive Full-Scale Drift vs Time

10 ppm of FS/1000 Hours typ

Gain Error

2, 8

See Note 3

Gain Drift vs. Temperature

2, 6, 9

2 ppm/°C max

Gain Drift vs. Time

10 ppm/1000 Hours typ

Bipolar Negative Full-Scale Error

See Note 3

Negative Full-Scale Drift vs. Temp

2, 6

2 ppm of FS/°C max

Power Supply Rejection 120 dB typ Measured with Zero Differential Voltage

Common-Mode Rejection (CMR) 120 dB min At DC. Measured with Zero Differential Voltage

Analog Input DC Bias Current

50 nA max

Analog Input DC Bias Current Drift

100 pA/°C typ

Analog Input DC Offset Current

10 nA max

Analog Input DC Offset Current Drift

50 pA/°C typ

STATIC PERFORMANCE (CHP = 0)

No Missing Codes 24 Bits min SKIP = 0

Output Noise and Update Rates See Tables III & IV

Integral Nonlinearity 18 ppm of FSR max

Offset Error See Note 3 Offset Error and Offset Drift Refer to Both

Offset Drift vs. Temperature

0.5 μV/°C typ Unipolar Offset and Bipolar Zero Errors

Offset Drift vs. Time

2.5 μV/1000 Hours typ

Positive Full-Scale Error

See Note 3

Positive Full-Scale Drift vs. Temp

6, 7

0.6 μV/°C typ

Positive Full-Scale Drift vs. Time

3 μV/1000 Hours typ

Gain Error

See Note 3

Gain Drift vs. Temperature

6, 9

2 ppm/°C typ

Gain Drift vs. Time

10 ppm/1000 Hours typ

Bipolar Negative Full-Scale Error See Note 3

Negative Full-Scale Drift vs. Temp 0.6 μV/°C typ

Power Supply Rejection 90 dB typ Measured with Zero Differential Voltage

Common-Mode Rejection (CMR) on AIN 100 dB typ At DC. Measured with Zero Differential Voltage

CMR on REF IN 120 dB typ At DC. Measured with Zero Differential Voltage

Analog Input DC Bias Current 60 nA max

Analog Input DC Bias Current Drift 150 pA/°C typ

Analog Input DC Offset Current 30 nA max

Analog Input DC Offset Current Drift 100 pA/°C typ

ANALOG INPUTS/REFERENCE INPUTS

Normal-Mode 50 Hz Rejection

88 dB min From 49 Hz to 51 Hz

Normal-Mode 60 Hz Rejection

88 dB min From 59 Hz to 61 Hz

Common-Mode 50 Hz Rejection

120 dB min From 49 Hz to 51 Hz

Common-Mode 60 Hz Rejection

120 dB min From 59 Hz to 61 Hz

Analog Inputs

Differential Input Voltage Ranges

Assuming 2.5 V or 5 V Reference with

HIREF Bit Set Appropriately

0 to +10 or ± 10 mV nom Gain = 250

0 to +20 or ± 20 mV nom Gain = 125

0 to +40 or ± 40 mV nom Gain = 62.5

0 to +80 or ± 80 mV nom Gain = 31.25

Absolute/Common-Mode Voltage

AGND + 1.2 V V min

– 0.95 V V max

Reference Input

REF IN(+) – REF IN(–) Voltage +2.5 V nom HIREF Bit of Mode Register = 0

REF IN(+) – REF IN(–) Voltage +5 V nom HIREF Bit of Mode Register = 1

Absolute/Common-Mode Voltage

AGND – 30 mV V min

+ 30 mV V max

NO REF Trigger Voltage 0.3 V min NO REF Bit Active If V

REF

Below This Voltage

0.65 V max NO REF Bit Inactive If V

REF

Above This Voltage

AD7730–SPECIFICATIONS

(AV

= +5 V, DV

= +3 V or +5 V; REF IN(+) = AV

; REF IN(–) = AGND = DGND =

0 V; f

CLK IN

= 4.9152 MHz. All specifications T

MIN

to T

MAX

unless otherwise noted.)

REV. B

–3–

AD7730/AD7730L

Parameter B Version

Units Conditions/Comments

LOGIC INPUTS

Input Current ± 10 μA max

All Inputs Except SCLK and MCLK IN

INL

, Input Low Voltage 0.8 V max DV

= +5 V

INL

, Input Low Voltage 0.4 V max DV

= +3 V

INH

, Input High Voltage 2.0 V min

SCLK Only (Schmitt Triggered Input)

T+

1.4/3 V min to V max DV

= +5 V

T+

1/2.5 V min to V max DV

= +3 V

T–

0.8/1.4 V min to V max DV

= +5 V

T–

0.4/1.1 V min to V max DV

= +3 V

T+

– V

T–

0.4/0.8 V min to V max DV

= +5 V

T+

– V

T–

0.4/0.8 V min to V max DV

= +3 V

MCLK IN Only

INL

, Input Low Voltage 0.8 V max DV

= +5 V

INL

, Input Low Voltage 0.4 V max DV

= +3 V

INH

, Input High Voltage 3.5 V min DV

= +5 V

INH

, Input High Voltage 2.5 V min DV

= +3 V

LOGIC OUTPUTS (Including MCLK OUT)

, Output Low Voltage I

SINK

= 800 μA Except for MCLK OUT

;

0.4 V max V

= +5 V

, Output Low Voltage I

SINK

= 100 μA Except for MCLK OUT

;

0.4 V max V

= +3 V

, Output High Voltage I

SOURCE

= 200 μA Except for MCLK OUT

;

4.0 V min V

= +5 V

, Output High Voltage I

SOURCE

= 100 μA Except for MCLK OUT

;

– 0.6 V V min V

= +3 V

Floating State Leakage Current ± 10 μA max

Floating State Output Capacitance

6 pF typ

TRANSDUCER BURNOUT

AIN1(+) Current –100 nA nom

AIN1(–) Current 100 nA nom

Initial Tolerance @ 25°C ± 10 % typ

Drift

0.1 %/°C typ

OFFSET (TARE) DAC

Resolution 6 Bit

LSB Size 2.3/2.6 mV min/mV max 2.5 mV Nominal with 5 V Reference (REF IN/2000)

DAC Drift

2.5 ppm/°C max

DAC Drift vs. Time

4, 16

25 ppm/1000 Hours typ

Differential Linearity –0.25/+0.75 LSB max Guaranteed Monotonic

SYSTEM CALIBRATION

Positive Full-Scale Calibration Limit

1.05 × FS V max FS Is the Nominal Full-Scale Voltage

(10 mV, 20 mV, 40 mV or 80 mV)

Negative Full-Scale Calibration Limit

–1.05 × FS V max

Offset Calibration Limit

–1.05 × FS V max

Input Span

0.8 × FS V min

2.1 × FS V max

POWER REQUIREMENTS

Power Supply Voltages

– AGND Voltage +4.75 to +5.25 V min to V max

Voltage +2.7 to +5.25 V min to V max With AGND = 0 V

Power Supply Currents External MCLK. Digital I/Ps = 0 V or DV

Current (Normal Mode) 10.3 mA max All Input Ranges Except 0 mV to +10 mV and ± 10 mV

Current (Normal Mode) 22.3 mA max Input Ranges of 0 mV to +10 mV and ± 10 mV Only

Current (Normal Mode) 1.3 mA max DV

of 2.7 V to 3.3 V

Current (Normal Mode) 2.7 mA max DV

of 4.75 V to 5.25 V

+ DV

Current (Standby Mode) 25 μA max Typically 10 μA. External MCLK IN = 0 V or DV

Power Dissipation AV

= DV

= +5 V. Digital I/Ps = 0 V or DV

Normal Mode 65 mW max All Input Ranges Except 0 mV to +10 mV and ± 10 mV

125 mW max Input Ranges of 0 mV to +10 mV and ± 10 mV Only

Standby Mode 125 μW max Typically 50 μW. External MCLK IN = 0 V or DV

REV. B

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P39 P40-P42 P43-P45 P46-P48 P49-P51 P52-P53

AD7730LBRZ

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Manufacturer:

Analog Devices Inc.

Description:

Analog to Digital Converters - ADC CMOS 24-Bit Low Pwr

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AD7730LBRZ

AD7730LBRZ

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