N64S830HA
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11
READ Status Register Instruction (RDSR)
This instruction provides the ability to read the
programmable bits of the Status Register. These register bits
may be read at any time by performing the following timing
sequence. Bits 0, 6 and 7 contain the data for the functional
operation and Bit 1 will read data type ‘1’ for the 64 Kb
device.
CS
Instruction
SI
04325169810711
SCK
7 6543210
High−Z
Status Register Data Out
SO
00 000 10
12 13 14 15
1
Figure 16. READ Status Register Instruction (RDSR)
Figure 17. Status Register
Bit 0Bit 1Bit 2Bit 3Bit 4Bit 5
Bit 6Bit 7
Hold Function
0 = Hold
1 = No Hold
Mode
0 0 = Word Mode
1 0 = Page Mode
0 1 = Burst Mode
1 1 = Reserved
0 0 0 0 1 = 64 Kb
Power−Up State
The serial SRAM enters a know state at power−up time. The device is in low−power standby state with CS = 1. A low level
on CS
is required to enter an active state.
