6
Figure 8. I
2
C-Bus Protocol.
A Acknowledge (0)
N Not Acknowledged (1)
P Stop Condition
R Read (1)
S Start Condition
Sr Repeated Start Condition
W Write (0)
… Continuation of protocol
Master-to-Slave
Slave-to-Master
171181811
S Slave Address W A Register Address A Data A ... P
I
2
C-Bus Write Protocol
171181171181
S Slave Address W A Register Address A Sr Slave Address R A Data A
811
Data A ... P
171181811
S Slave Address R A Data A Data A ... P
I
2
C-Bus Read Protocol
The I
2
C-bus standard provides for three types of bus
transactions: read, write, and a combined protocol.
During a write operation, the rst byte written is a
command byte followed by data. In a combined protocol,
the rst byte written is the command byte followed by
reading a series of bytes. If a read command is issued,
the register address from the previous command is used
for data access. Likewise, if the MSB of the command is
not set, the device writes a series of bytes at the address
stored in the last valid command with a register address.
The command byte contains either control information
or a 5-bit register address. The control commands can
also be used to clear interrupts.
The I
2
C-bus protocol was developed by Philips (now
NXP). For a complete description of the I
2
C-bus protocol,
review the NXP I
2
C-bus design speci cation at http://
www.i2c−bus.org/references/.
I
2
C-Bus Protocol
Interface and control are accomplished through an I
2
C-
bus serial compatible interface (standard or fast mode)
to a set of registers that provide access to device control
functions and output data. The devices support the 7-bit
I
2
C-bus addressing protocol.
The device supports a single slave address of 0×73 Hex
using the 7-bit addressing protocol.
I
2
C-Bus Read Protocol – Combined Format
