Pin description STA8088FG
10/17 Doc ID 022731 Rev 3
2.5 Test/emulated dedicated pins
2.6 RF front-end pins
2.7 Port 0 pins
Port 0 consists of a 32-bit bidirectional I/O port (only 3-bit are used in STA8088FG).
It can be either used as general purpose Input or Output port, or configured according to the
associated alternate functions.
CAN0TX
(1)
VDD_IOR5 O CAN0 - transmit data output 51
CAN0RX
(1)
VDD_IOR5 I CAN0 - receive data input 54
1. Only for STA8088FGB (see Figure 5: Ordering information scheme).
Table 2. Main function pins (continued)
Symbol I/O voltage I/O Functions VFQFPN56
Table 3. Test/emulated dedicated pins
Symbol I/O voltage I/O Functions VFQFPN56
TDO VDD_IOR5 O JTAG test data out 50
TDI VDD_IOR5 I JTAG test data in 53
TCK VDD_IOR5 I JTAG test clock 56
TMS VDD_IOR5 I JTAG test mode select 2
TRSTn VDD_IOR5 I JTAG test circuit reset 3
TP_IF_P VRF12_IF O Diff. test point for IF – positive 5
TP_IF_N VRF12_IF O Diff. test point for IF – negative 6
Table 4. RF front-end pins
Symbol I/O voltage I/O Functions VFQFPN56
LNA_IN VRF12_LNA I Low noise amplifier input 9
LNA_OUT VRF12_LNA O Low noise amplifier output 11
RFA_IN VRF12_RFA I RF amplifier input 15
XTAL_In VRF12_RFDig I Input side of crystal oscillator or TCXO input 19
XTAL_Out VRF12_RFDig O Output side of crystal oscillator 20
STA8088FG Pin description
Doc ID 022731 Rev 3 11/17
2.8 Port 1 pins
Port 1 consists of a 32-bit bidirectional I/O port (only9-bit are used in STA8088FG).
It can be either used as general purpose Input or Output port, or configured according to the
associated alternate functions.
Table 5. Port 0 pins
Symbol I/O voltage I/O Mode Functions VFQFPN56
P0.0 VDD_IOR1
IO Default GPIO.0: General Purpose IO
35
I A PPS_IN: Pulse Per Second Input
O B PPS_OUT: Pulse Per Second Output
O C SSP_CSN: SSP Chip Select Active Low
P0.8 VDD_IOR5
O Default CAN1TX
(1)
: CAN1 Transmit Data Output
55IO A GPIO.8: General Purpose IO
IO B I2C_SD: I2C Serial Data
P0.9 VDD_IOR5
I Default CAN1RX
(1)
: CAN 1 Receive Data Input
1IO A GPIO.9: General Purpose IO
O B I2C_SCLK: I2C Clock
1. Only for STA8088FGB (see Figure 5: Ordering information scheme).
Table 6. Port 1 pins
Symbol I/O Voltage I/O Mode Functions VFQFPN56
P1.0 VDD_IOR1
O Default
SSP_CSN/IOPWRSEL_R1: SSP chip select active
low / I/O Ring 1 power selection
40
I/O A GPIO32: general purpose I/O
I/O B SIGNGGPS: GGPS 3-bit coding output (sign)
O C SQI_CEN: SQI Flash chip enable
P1.1 VDD_IOR1
I/O Default SSP_CLK: SSP clock
41
I/O A GPIO33: general purpose I/O
I/O B CLOCK_GGPS: GGPS clock out
O C SQI_CLK: SQI Flash clock
P1.2 VDD_IOR1
I Default SSP_DI: SSP serial data input
42
I/O A GPIO34: general purpose I/O
I/O B SIGNGNS: GNS 3-bit coding output (sign)
IO C SQI_SIO0/SI: SQI Flash data I/O 0 / serial I
Pin description STA8088FG
12/17 Doc ID 022731 Rev 3
P1.3 VDD_IOR1
O Default SSP_DO: SSP serial data output
43
I/O A GPIO35: general purpose I/O
I/O B CLOCK_GNS: GNS clock out
IO C SQI_SIO1/SO: SQI Flash data I/O 1 / serial O
P1.4 VDD_IOR1
I Default UART2_RX: UART 2 Rx data
36
I/O A GPIO36: general purpose I/O
P1.5 VDD_IOR1
I/O Default UART2_TX / BOOT_0: UART 2 Tx data / ARM Boot 0
37
I/O A GPIO37: general purpose I/O
P1.6 VDD_IOR1
I Default UART0_RX: UART 0 Rx data
38I/O A GPIO38: general purpose I/O
I/O C SQI_SIO2: SQI Flash data I/O 2
P1.7 VDD_IOR1
I/O Default UART0_TX / BOOT_1: UART 0 Tx data / ARM Boot 1
39I/O A GPIO39: general purpose I/O
I/O C SQI_SIO3: SQI Flash data I/O 3
P1.21 VDD_IOR3 I/O A GPIO53: general purpose I/O 46
Table 6. Port 1 pins (continued)
Symbol I/O Voltage I/O Mode Functions VFQFPN56

STA8088FG

Mfr. #:
Manufacturer:
STMicroelectronics
Description:
RF Receiver Fully Integrated GPS/Galileo/Glonass/QZSS Receiver with embedded RF and in-package Flash
Lifecycle:
New from this manufacturer.
Delivery:
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