REV. C–4–
AD674B/AD774B
TIMING—STAND ALONE MODE (Figures 4a and 4b)
J, K, A, B Grades T Grade
Parameter Symbol Min Typ Max Min Typ Max Unit
Data Access Time t
DDR
150 150 ns
Low R/C Pulsewidth t
HRL
50 50 ns
STS Delay from R/C t
DS
200 225 ns
Data Valid After R/C Low t
HDR
25 25 ns
STS Delay After Data Valid t
HS
30 200 600 30 200 600 ns
High R/C Pulsewidth t
HRH
150 150 ns
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS*
V
CC
to Digital Common . . . . . . . . . . . . . . . . . . . 0 to +16.5 V
V
EE
to Digital Common . . . . . . . . . . . . . . . . . . . . 0 to 16.5 V
V
LOGIC
to Digital Common . . . . . . . . . . . . . . . . . . . 0 to +7 V
Analog Common to Digital Common . . . . . . . . . . . . . . . ± 1 V
Digital Inputs to Digital Common . . . 0.5 V to V
LOGIC
+0.5 V
Analog Inputs to Analog Common . . . . . . . . . . . . V
EE
to V
CC
20 V
IN
to Analog Common . . . . . . . . . . . . . . . . . . . . . . ± 24 V
REF OUT . . . . . . . . . . . . . . . . . . Indefinite Short to Common
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Momentary Short to V
CC
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 175°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . 825 mW
Lead Temperature, Soldering (10 sec) . . . . . . . . . . . . . 300°C
Storage Temperature . . . . . . . . . . . . . . . . . . 65°C to +150°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
R/C
STS
DB11DB0
DATA
VAL ID
DATA VALID
t
HRL
t
DS
HIGHZ
t
HS
t
HDR
t
C
Flgure 4a. Standalone Mode Timing Low Pulse R/
C
R/C
STS
DB11DB0
HIGHZ HIGHZ
DATA
VAL ID
t
HRH
t
DS
t
DDR
t
HDR
t
C
t
HL
Figure 4b. Standalone Mode Timing High Pulse for R/
C
WARNING!
ESD SENSITIVE DEVICE
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD674B/AD774B features proprietary ESD protection circuitry, permanent damage may occur
on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
ORDERING GUIDE
Conversion INL Package Package
Model
l
Temperature Time (max) (T
MIN
to T
MAX
) Description Option
2
AD674BJN 0°C to 70°C 15 µs ± 1 LSB Plastic DIP N-28
AD674BKN 0°C to 70°C 15 µs ±1/2 LSB Plastic DIP N-28
AD674BAR 40°C to +85°C 15 µs ±1 LSB Plastic SOIC R-28
AD674BBR 40°C to +85°C 15 µs ± 1/2 LSB Plastic SOIC R-28
AD674BAD 40°C to +85°C 15 µs ±1 LSB Ceramic DIP D-28
AD674BBD 40°C to +85°C 15 µs ±1/2 LSB Ceramic DIP D-28
AD674BTD 55°C to +125°C 15 µs ± 1 LSB Ceramic DIP D-28
AD774BJN 0°C to 70°C8 µs ±1 LSB Plastic DIP N-28
AD774BKN 0°C to 70°C8 µs ± 1/2 LSB Plastic DIP N-28
AD774BAR 40°C to +85°C8 µs ±1 LSB Plastic SOIC R-28
AD774BBR 40°C to +85°C8 µs ±1/2 LSB Plastic SOIC R-28
AD774BAD 40°C to +85°C8 µs ± 1 LSB Ceramic DIP D-28
AD774BBD 40°C to +85°C8 µs ± 1/2 LSB Ceramic DIP D-28
AD774BTD 55°C to +125°C8 µs ± 1 LSB Ceramic DIP D-28
NOTES
1
For details on grade and package offerings screened in accordance with MIL-STD-883, refer to the Analog Devices Military
Products Databook or the current AD674B/ AD774B/883B data sheet.
2
N = Plastic DIP; D = Hermetic DIP; R = Plastic SOIC.
REV. C
–5–
DEFINITION OF SPECIFICATIONS
Linearity Error
Linearity error refers to the deviation of each individual code
from a line drawn from zero through full scale. The point
used as zero occurs 1/2 LSB (1.22 mV for 10 V span) before
the first code transition (all zeroes to only the LSB on). Full
scale is defined as a level 1 1/2 LSB beyond the last code tran-
sition (to all ones). The deviation of a code from the true straight
line is measured from the middle of each particular code.
The K, B, and T grades are guaranteed for maximum nonlinear-
ity of ± 1/2 LSB. For these grades, this means that an analog
value that falls exactly in the center of a given code width will
result in the correct digital output code. Values nearer the upper
or lower transition of the code width may produce the next upper
or lower digital output code. The J and A grades are guaranteed
to ± 1 LSB max error. For these grades, an analog value that
falls within a given code width will result in either the correct
code for that region or either adjacent one.
Note that the linearity error is not user adjustable.
Differential Linearity Error (No Missing Codes)
A specification that guarantees no missing codes requires that
every code combination appear in a monotonic increasing sequence
as the analog input level is increased. Thus every code must have a
finite width. The AD674B and AD774B guarantee no missing codes
to 12-bit resolution, requiring that all 4096 codes must be present
over the entire operating temperature ranges.
Unipolar Offset
The first transition should occur at a level 1/2 LSB above analog
common. Unipolar offset is defined as the deviation of the actual
transition from that point. This offset can be adjusted as discussed
later. The unipolar offset temperature coefficient specifies the
maximum change of the transition point over temperature,
with or without external adjustment.
Bipolar Offset
In the bipolar mode the major carry transition (0111 1111 1111
to 1000 0000 0000) should occur for an analog value 1/2 LSB
below analog common. The bipolar offset error and temperature
coefficient specify the initial deviation and maximum change in
the error over temperature.
Quantization Uncertainty
Analog-to-digital converters exhibit an inherent quantization
uncertainty of ±1/2 LSB. This uncertainty is a fundamental
characteristic of the quantization process and cannot be reduced
for a converter of given resolution.
Left-Justified Data
The output data format is left-justified. This means that the
data represents the analog input as a fraction of full scale, rang-
ing from 0 to 4095/4096. This implies a binary point 4095 to
the left of the MSB.
Full-Scale Calibration Error
The last transition (from 1111 1111 1110 to 1111 1111 1111)
should occur for an analog value 1 1/2 LSB below the nominal
full scale (9.9963 V for 10.000 V full scale). The full-scale cali-
bration error is the deviation of the actual level at the last transi-
tion from the ideal level. This error, which is typically 0.05% to
0.1% of full scale, can be trimmed out as shown in Figures 7
and 8. The full-scale calibration error over temperature is given
with and without the initial error trimmed out. The temperature
coefficients for each grade indicate the maximum change in the
full-scale gain from the initial value using the internal 10 V
reference.
Temperature Drift
The temperature drift for full-scale calibration, unipolar offset,
and bipolar offset specifies the maximum change from the initial
(25°C) value to the value at T
MIN
or T
MAX
.
Power Supply Rejection
The standard specifications assume use of +5.00 V and ± 15.00 V
or ± 12.00 V supplies. The only effect of power supply error on
the performance of the device will be a small change in the
full-scale calibration. This will result in a linear change in all
low-order codes. The specifications show the maximum full-
scale change from the initial value with the supplies at the
various limits.
Code Width
A fundamental quantity for A/D converter specifications is the
code width. This is defined as the range of analog input values for
which a given digital output code will occur. The nominal value
of a code width is equivalent to 1 least significant bit (LSB) of the
full-scale range or 2.44 mV out of 10 V for a 12-bit ADC.
AD674B/AD774B
REV. C–6–
AD674B/AD774B
PIN FUNCTION DESCRIPTIONS
Symbol Pin No. Type* Name and Function
AGND 9 P Analog Ground (Common)
A
0
4 DI Byte Address/Short Cycle. If a conversion is started with A
0
Active LOW, a full 12-bit conversion
cycle is initiated. If A
0
is Active HIGH during a convert start, a shorter 8-bit conversion cycle
results. During Read (R/C = 1) with 12/8 LOW, A
0
= LOW enables the 8 most significant bits,
and A
0
= HIGH enables DB3DB0 and sets DB7DB4 = 0.
BIP OFF 12 AI Bipolar Offset. Connect through a 50 resistor to REF OUT for bipolar operation or to Analog
Common for unipolar operation.
CE 6 DI Chip Enable. Chip Enable is Active HIGH and is used to initiate a convert or read operation.
CS 3 DI Chip Select. Chip Select is Active LOW.
DB11DB8 2724 DO Data Bits 11 through 8. In the 12-bit format (see 12/8 and A
0
pins) these pins provide the upper
4 bits of data. In the 8-bit format, they provide the upper 4 bits when A
0
is LOW and are
disabled when A
0
is HIGH.
DB7DB4 2320 DO Data Bits 7 through 4. In the 12-bit format these pins provide the middle 4 bits of data. In the
8-bit format they provide the middle 4 bits when A
0
is LOW and all zeroes when A
0
is HIGH.
DB3DB0 1916 DO Data Bits 3 through 0. In both the 12-bit and 8-bit format these pins provide the lower 4 bits of
data when A
0
is HIGH; they are disabled when A
0
is LOW.
DGND 15 P Digital Ground (Common)
REF OUT 8 AO 10 V Reference Output
R/C 5 DI Read/Convert. In the full control mode R/C is Active HIGH for a read operation and Active LOW
for a convert operation. In the standalone mode, the falling edge of R/C initiates a conversion.
REF IN 10 AI Reference Input is connected through a 50 resistor to +10 V Reference for normal operation.
STS 28 DO Status is Active HIGH when a conversion is in progress and goes LOW when the conversion is
completed.
V
CC
7 P +12 V/+15 V Analog Supply
V
EE
11 P 12 V/15 V Analog Supply
V
LOGIC
1 P 5 V Logic Supply
10 V
IN
13 AI 10 V Span Input, 0 V to +10 V unipolar mode or 5 V to +5 V bipolar mode. When using the
20 V Span, 10 V
IN
should not be connected.
20 V
IN
14 AI 20 V Span Input, 0 V to +20 V unipolar mode or 10 V to +10 V bipolar mode. When using the
10 V Span, 20 V
IN
should not be connected.
12/8 2 DI The 12/8 pin determines whether the digital output data is to be organized as two 8-bit words
(12/8 LOW) or a single 12-bit word (12/8 HIGH).
*Types: AI = Analog Input, AO = Analog Output, DI = Digital Input, DO = Digital Output, P = Power
PIN CONFIGURATION
TOP VIEW
(Not to Scale)
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
AD674B
OR
AD774B
V
LOGIC
12/8
CS
A
0
R/C
CE
V
CC
REF OUT
AGND
REF IN
V
EE
BIP OFF
10 V
IN
20 V
IN
STS
DB11 (MSB)
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0 (LSB)
DGND

AD774BARZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC IC 12-Bit Successive Approx
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union