REV. C
–7–
CIRCUIT OPERATION
The AD674B and AD774B are complete 12-bit monolithic A/D
converters that require no external components to provide the
complete successive-approximation analog-to-digital conversion
function. A block diagram is shown in Figure 5.
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
AD674B/AD774B
5V SUPPLY
V
LOGIC
DATA MODE SELECT
12/8
CHIP SELECT
CS
BYTE ADDRESS/
SHORT CYCLE A
0
READ/CONVERT R/C
CHIP ENABLE
CE
12V/15V SUPPLY
V
CC
10V REFERENCE
REF OUT
ANALOG COMMON
AC
REFERENCE INPUT
REF IN
12V/15V SUPPLY
V
EE
BIPOLAR OFFSET
BIPOFF
10V SPAN INPUT
10V
IN
20V SPAN INPUT
20V
IN
STATUS
STS
DB11 (MSB)
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0 (LSB)
DIGITAL
COMMON DC
CONTROL
VO LTAG E
DIVIDER
N
Y
B
B
L
E
A
MSB
3
S
T
A
T
E
O
U
T
P
U
T
B
U
F
F
E
R
S
LSB
N
Y
B
B
L
E
B
N
Y
B
B
L
E
C
CLOCK SAR
12
10V
REF
+
COMP
I DAC
+
199.95
k
DAC
N
V
EE
I REF
DIGITAL
DATA
OUTPUTS
Figure 5. Block Diagram of AD674B and AD774B
When the control section is commanded to initiate a conversion
(as described later) it enables the clock and resets the
successive-approximation register (SAR) to all zeroes. Once a
conversion cycle has begun, it cannot be stopped or restarted
and data is not available from the output buffers. The SAR,
timed by the clock, will sequence through the conversion cycle
and return an end-of-convert flag to the control section. The
control section will then disable the clock, bring the output
status flag low, and enable control functions to allow data read
by external command.
During the conversion cycle, the internal 12-bit current output
DAC is sequenced by the SAR from the most significant bit
(MSB) to least significant bit (LSB) to provide an output cur-
rent that accurately balances the input signal current through
the divider network. The comparator determines whether the
addition of each successively weighted bit current causes the
DAC current sum to be greater or less than the input current; if
the sum is less, the bit is left on; if more, the bit is turned off.
After testing all the bits, the SAR contains a 12-bit binary code
that accurately represents the input signal to within ± 1/2 LSB.
The temperature-compensated reference provides the primary
voltage reference to the DAC and guarantees excellent stability
with both time and temperature. The reference is trimmed to
10.00 V ± 1%; it can supply up to 2.0 mA to an external load in
addition to the requirements of the reference input resistor
(0.5 mA) and bipolar offset resistor (0.5 mA). Any external load
on the reference must remain constant during conversion. The
thin-film application resistors are trimmed to match the full-
scale output current of the DAC. The input divider network
provides a 10 V or 20 V input range. The bipolar offset resistor
is grounded for unipolar operation and connected to the 10 V
reference for bipolar operation.
DRIVING THE ANALOG INPUT
The AD674B and AD774B are successive-approximation analog-
to-digital converters. During the conversion cycle, the ADC input
current is modulated by the DAC test current at approximately
a 1 MHz rate. Thus it is important to recognize that the signal
source driving the ADC must be capable of holding a constant
output voltage under dynamically changing load conditions.
CURRENT
OUTPUT
DAC
ANALOG COMMON
CURRENT
LIMITING
RESISTORS
FEEDBACK TO AMPLIFIER
ADC
COMPARATOR
I
IN
I
TEST
R
IN
I
DIFF
I
IN
IS MODULATED BY
CHANGES IN TEST CURRENT.
AMPLIFIER PULSE LOAD
RESPONSE LIMITED BY
OPEN-LOOP OUTPUT IMPEDANCE.
V
V+
SAR
Figure 6. Op Amp—ADC Interface
The closed-loop output impedance of an op amp is equal to the
open-loop output impedance (usually a few hundred ohms)
divided by the loop gain at the frequency of interest. It is often
assumed that the loop gain of a follower-connected op amp is
sufficiently high to reduce the closed-loop output impedance to
a negligibly small value, particularly if the signal is low fre-
quency. However, the amplifier driving the ADC must either
have sufficient loop gain at 1 MHz to reduce the closed-loop
output impedance to a low value or have low open-loop output
impedance. This can be accomplished by using a wideband op
amp, such as the AD711.
If a sample-hold amplifier is required, the monolithic AD585 or
AD781 is recommended, with the output buffer driving the
AD674B or AD774B input directly. A better alternative is the
AD1674, which is a 10 µs sampling ADC in the same pinout as the
AD574A, AD674A, or AD774B and is functionally equivalent.
SUPPLY DECOUPLING AND LAYOUT
CONSIDERATION
It is critical that the power supplies be filtered, well regulated,
and free from high-frequency noise. Use of noisy supplies will
cause unstable output codes. Switching power supplies is not
recommended for circuits attempting to achieve 12-bit accuracy
unless great care is used in filtering any switching spikes present
in the output. Few millivolts of noise represent several counts of
error in a 12-bit ADC.
Decoupling capacitors should be used on all power supply pins;
the 5 V supply decoupling capacitor should be connected directly
from Pin 1 to Pin 15 (digital common) and the +V
CC
and V
EE
pins should be decoupled directly to analog common (Pin 9). A
suitable decoupling capacitor is a 4.7 µF tantalum type in paral-
lel with a 0.1 µF ceramic disc type.
AD674B/AD774B
REV. C–8–
AD674B/AD774B
Circuit layout should attempt to locate the ADC, associated
analog input circuitry, and interconnections as far as possible
from logic circuitry. For this reason, the use of wire-wrap circuit
construction is not recommended. Careful printed-circuit layout
and manufacturing is preferred.
UNIPOLAR RANGE CONNECTIONS FOR THE AD674B
AND AD774B
The AD674B and AD774B contain all the active components
required to perform a complete 12-bit A/D conversion. Thus,
for most situations, all that is necessary is connection of the
power supplies (+5 V, +12/+15 V, and 12/15 V), the analog
input, and the conversion initiation command, as discussed on
the next page.
2
3
4
5
6
8
12
13
10
14
9
AD674B/AD774B
STS 28
HIGH BITS
2427
MIDDLE BITS
2023
LOW BITS
1619
+15V 7
15V 11
DIG COM 15
+5V 1
100
R2
GAIN
R1
100k
OFFSET
+12V/
+15V
12V/
15V
100k
100
0 TO 10V
ANALOG
INPUTS
0 TO 20V
12/8
CS
A
0
R/C
CE
REF OUT
BIP OFF
10V
IN
REF IN
20V
IN
ANA COM
Figure 7. Unipolar Input Connections
All of the thin-film application resistors of the AD674B and
AD774B are factory trimmed for absolute calibration. Therefore,
in many applications, no calibration trimming will be required.
The absolute accuracy for each grade is given in the specification
tables. For example, if no trims are used, ± 2 LSB max zero offset
error and ± 0.25% (10 LSB) max full-scale error are guaranteed.
If the offset trim is not required, Pin 12 can be connected directly
to Pin 9; the two resistors and trimmer for Pin 12 are then not
needed. If the full-scale trim is not required, a 50 1% metal
film resistor should be connected between Pin 8 and Pin 10.
The analog input is connected between Pins 13 and 9 for a 0 V
to 10 V input range, between Pins 14 and 9 for a 0 V to 20 V
input range. Input signals beyond the supplies are easily accommo-
dated. For the 10 V span input, the LSB has a nominal value of
2.44 mV; for the 20 V span, 4.88 mV. If a 10.24 V range is
desired (nominal 2.5 mV/bit), the gain trimmer (R2) should be
replaced by a 50 resistor and a 200 trimmer inserted in
series with the analog input to Pin 13 (for a full-scale range of
20.48 V [5 mV/bit] use a 500 trimmer into Pin 14). The
gain trim described below is now done with these trimmers.
The nominal input impedance into Pin 13 is 5 k, and into Pin
14 is 10 k.
UNIPOLAR CALIBRATION
The connections for unipolar ranges are shown in Figure 7. The
AD674B or AD774B is trimmed to a nominal 1/2 LSB offset so
that the exact analog input for a given code will be in the middle
of that code (halfway between the transitions to the codes above
and below it). Thus, when properly calibrated, the first transition
(from 0000 0000 0000 to 0000 0000 0001) will occur for an input
level of +1/2 LSB (1.22 mV for 10 V range).
If Pin 12 is connected to Pin 9, the unit will behave in this manner,
within specifications. If the offset trim (R1) is used, it should be
trimmed as above, although a different offset can be set for a
particular system requirement. This circuit will give approximately
± 15 mV of offset trim range.
The full-scale trim is done by applying a signal 1 1/2 LSB below
the nominal full scale (9.9963 for a 10 V range). Trim R2 to
give the last transition (1111 1111 1110 to 1111 1111 1111).
BIPOLAR OPERATION
The connections for bipolar ranges are shown in Figure 8.
Again, as for the unipolar ranges, if the offset and gain specifica-
tions are sufficient, one or both of the trimmers shown can be
replaced by a 50 ± 1% fixed resistor. The analog input is
applied as for the unipolar ranges. Bipolar calibration is similar
to unipolar calibration. First, a signal 1/2 LSB above negative
full scale (4.9988 V for the ±5 V range) is applied and R1 is
trimmed to give the first transition (0000 0000 0000 to 0000
0000 0001). Then a signal 1 1/2 LSB below positive full scale
(+4.9963 V for the ±5 V range) is applied and R2 trimmed to
give the last transition (1111 1111 1110 to 1111 1111 1111).
AD674B/AD774B
HIGH BITS
2427
MIDDLE BITS
2023
LOW BITS
1619
100
R2
GAIN
ANALOG
INPUTS
10V
R1
100
OFFSET
5V
2
3
4
5
6
8
12
13
10
14
9
STS 28
+15V 7
15V 11
DIG COM 15
+5V 1
12/8
CS
A
0
R/C
CE
REF OUT
BIP OFF
10V
IN
REF IN
20V
IN
ANA COM
Figure 8. Bipolar Input Connections
GROUNDING CONSIDERATIONS
The analog common at Pin 9 is the ground reference point for
the internal reference and is thus the high quality ground for
the ADC; it should be connected directly to the analog reference
point of the system. To achieve the high-accuracy performance
available from the ADC in an environment of high digital noise
content, the analog and digital commons must be connected
together at the package. In some situations, the digital common
at Pin 15 can be connected to the most convenient ground ref-
erence point; digital power return is preferred.
REV. C
–9–
TO
OUTPUT
BUFFERS
CE
CS
R/C
A
0
12/8
NYBBLE A
ENABLE
NYBBLE B
ENABLE
NYBBLE C
ENABLE
NYBBLE = 0
ENABLE
STATUS
CLK EN
HIGH IF CONVERSION
IN PROGRESS
SAR
RESET
EOC 12
EOC 8
START CONVERT
S
R
Q
QB
READ
VALUE OF A
0
AT LAST CONVERT COMMAND
D
EN
D
EN
Q
R
S
Q
Figure 9. Equivalent Internal Logic Circuitry
CONTROL LOGIC
The AD674B and AD774B contain on-chip logic to provide
conversion initiation and data read operations from signals
commonly available in microprocessor systems; this internal
logic circuitry is shown in Figure 9.
The control signals CE, CS, and R/C control the operation of
the converter. The state of R/C when CE and CS are both
asserted determines whether a data read (R/C = 1) or a convert
(R/C = 0) is in progress. The register control inputs, A
0
and
12/8, control conversion length and data format. If a conversion
is started with A
0
low, a full 12-bit conversion cycle is initiated.
If A
0
is high during a convert start, a shorter 8-bit conversion
cycle results. During data read operations, A
0
determines
whether the three-state buffers containing the 8 MSBs of the
conversion result (A
0
= 0) or the 4 LSBs (A
0
= 1) are enabled.
The 12/8 pin determines whether the output data is to be orga-
nized as two 8-bit words (12/8 tied to DIGITAL COMMON)
or a single 12-bit word (12/8 tied to V
LOGIC
). In the 8-bit mode,
the byte addressed when A
0
is high contains the 4 LSBs from
the conversion followed by four trailing zeroes. This organiza-
tion allows the data lines to be overlapped for direct interface to
8-bit buses without the need for external three-state buffers.
An output signal, STS, indicates the status of the converter.
STS goes high at the beginning of a conversion and returns low
when the conversion cycle is complete.
Table I. Truth Table
CE CS R/C 12/8 A
0
Operation
0XXXXNone
X1 XXXNone
1 0 0 X 0 Initiate 12-Bit Conversion
1 0 0 X 1 Initiate 8-Bit Conversion
1011XEnable 12-Bit Parallel Output
10100Enable 8 Most Significant Bits
10101Enable 4 LSBs + 4 Trailing Zeroes
The ADC may be operated in one of two modes, the full-control
mode and the standalone mode. The full-control mode uses all
the control signals and is useful in systems that address decode
multiple devices on a single data bus. The standalone mode is
useful in systems with dedicated input ports available. In gen-
eral, the standalone mode is capable of issuing start-convert
commands on a more precise basis and therefore produces
higher accuracy results. The following sections describe these
two modes in more detail.
FULL-CONTROL MODE
Chip Enable (CE), Chip Select (CS), and Read/Convert (R/C)
are used to control Convert or Read modes of operation. Either
CE or CS may be used to initiate a conversion. The state of R/C
when CE and CS are both asserted determines whether a data
Read (R/C = 1) or a Convert (R/C = 0) is in progress. R/C
should be LOW before both CE and CS are asserted; if R/C is
HIGH, a Read operation will momentarily occur, possibly
resulting in system bus contention.
AD674B/AD774B

AD774BARZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC IC 12-Bit Successive Approx
Lifecycle:
New from this manufacturer.
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