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Figure 3 Typical Power up sequence where DVDD is powered before AVDD
Figure 4 Typical Power up sequence where AVDD is powered before DVDD
Typical POR Operation (typical values, not tested)
SYMBOL MIN TYP MAX UNIT
V
pora
0.5 0.7 1.0 V
V
porr
0.5 0.7 1.1 V
V
pora_off
1.0 1.4 2.0 V
V
pord_off
0.6 0.8 1.0 V
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In a real application the designer is unlikely to have control of the relative power up sequence of
AVDD and DVDD. Using the POR circuit to monitor CAP ensures a reasonable delay between
applying power to the device and Device Ready.
Figure 3 and Figure 4 show typical power up scenarios in a real system. Both AVDD and DVDD must
be established and CAP must have reached the threshold V
porr
before the device is ready and can be
written to. Any writes to the device before Device Ready will be ignored.
Figure 3 shows DVDD powering up before AVDD. Figure 4 shows AVDD powering up before DVDD.
In both cases, the time from applying power to Device Ready is dominated by the charge time of
CAP.
A 10uF cap is recommended for decoupling on CAP. The charge time for CAP will dominate the time
required for the device to become ready after power is applied. The time required for VMIDADC to
reach the threshold is a function of the CAP resistor string and the decoupling capacitor. The
Resistor string has a typical equivalent resistance of 50k (+/-20%). Assuming a 10uF capacitor, the
time required for CAP to reach threshold of 1V is approx 110ms.
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DEVICE DESCRIPTION
INTRODUCTION
The WM8738 is an ADC designed for audio recording. It’s features, performance and low power
consumption make it ideal for recordable CD or DVD players, karaoke, MP3 players and mini-disc
players.
The on-board stereo analogue to digital converter (ADC) is of a high quality using a multi-bit high-
order oversampling architecture delivering optimum performance with low power consumption. The
ADC includes a selectable digital high pass filter to remove unwanted DC components from the audio
signal. The device supports system clock inputs of 256, 384, 512fs or 768fs (fs is the sampling rate)
The output from the ADC is available on the digital audio interface in either I
2
S or left justified audio
data formats.
The line inputs are biased internally through the operational amplifier to V
CAP
.
ADC
The WM8738 uses a multi-bit over sampled sigma-delta ADC. A single channel of the ADC is
illustrated in Figure 3.
LIN/RIN
ANALOG
INTEGRATOR
MULTI
BITS
TO ADC DIGITAL FILTERS
Figure 3 Multi-Bit Oversampling Sigma Delta ADC Schematic
The use of multi-bit feedback and high oversampling rates reduces the effects of jitter and high
frequency noise.
The ADC Full Scale input is 1.0V rms at AVDD = 5.0 volts. Any voltage greater than full scale will
possibly overload the ADC and cause distortion. Note that the full scale input tracks directly with
AVDD.
The ADC filters perform true 24 bit signal processing to convert the raw multi-bit oversampled data
from the ADC to the correct sampling frequency to be output on the digital audio interface.
ADC DIGITAL FILTER
The ADC digital filters contain a digital high pass filter, selectable via pin NOHP.
NOHP = 0 Digital high pass filter enabled
NOHP = 1 Digital high pass filter bypassed
The high-pass filter response detailed in Digital Filter Characteristics. The operation of the high pass
filter removes residual DC offsets that are present on the audio signal.

WM8738CGED/R

Mfr. #:
Manufacturer:
Cirrus Logic
Description:
Audio A/D Converter ICs Stereo ADC Low Power
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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