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WM8738CGED/R

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WM8738 Production Data
w
PD, Rev 4.5, February 2012
7
TERMINOLOGY
1. Signal-to-noise ratio (dB) - SNR is a measure of the difference in level between the full scale output and the output with
no signal applied. (No ‘Auto-zero’ or Automute function is employed in achieving these results).
2. Dynamic range (dB) - DNR is a measure of the difference between the highest and lowest portions of a signal.
Normally a THD+N measurement at 60dB below full scale. The measured signal is then corrected by adding the 60dB
to it. (e.g. THD+N @ -60dB= -32dB, DR= 92dB).
3. THD (dB) - THD is a ratio, of the r.m.s. values, of Distortion/Signal.
4. Stop band attenuation (dB) - Is the degree to which the frequency spectrum is attenuated (outside audio band).
5. Channel Separation (dB) - Also known as Cross-Talk. This is a measure of the amount one channel is isolated from
the other. Normally measured by sending a full scale signal down one channel and measuring the other.
6. Pass-Band Ripple - Any variation of the frequency response in the pass-band region.
WM8738 Production Data
w
PD, Rev 4.5, February 2012
8
DIGITAL AUDIO INTERFACE TIMING
MCLK
t
MC LK H
t
MCL KY
t
MC LK L
Figure 1 Master Clock Timing Requirements
Test Conditions
AVDD = 5.0V, AGND = 0V, DVDD = 3.3V, DGND = 0V, T
A
= +25
o
C, fs = 48kHz, MCLK = 256fs unless otherwise stated.
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
System Clock Timing Information
MCLK System clock pulse width high
T
MCLKH
10 ns
MCLK System clock pulse width low
T
MCLKL
10 ns
MCLK System clock cycle time
T
MCLKY
27 ns
BCLK
LRCLK
t
BCH
t
BCL
t
BCY
SDATO
t
LRSU
t
LRH
t
DD
Figure 2 Digital Audio Data Timing
Test Conditions
AVDD = 5.0V, AGND = 0V, DVDD = 3.3V, DGND = 0V, T
A
= +25
o
C, fs = 48kHz, MCLK = 256fs unless otherwise stated.
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
Audio Data Input Timing Information
BCLK cycle time
t
BCY
80 ns
BCLK pulse width high
t
BCH
40 ns
BCLK pulse width low
t
BCL
40 ns
LRCLK set-up time to BCLK
rising edge
t
LRSU
10 ns
LRCLK hold time from
BCLK rising edge
t
LRH
10 ns
SDATO propagation delay
from BCLK falling edge
t
DD
10 ns
WM8738 Production Data
w
PD, Rev 4.5, February 2012
9
INTERNAL POWER ON RESET CIRCUIT
Power On Reset
Circuit
AVDD
100K
100K
CAP
DVDD
INTERNAL PORB
VDD
T1
T2
Figure 2 Internal Power On Reset Circuit Schematic
The WM8738 includes an internal Power On Reset Circuit which is used reset the digital logic into a
default state after power up.
Figure 2 shows a schematic of the internal POR circuit. The circuit monitors DVDD and CAP and
asserts PORB low if DVDD or CAP are below the minimum threshold V
por_off
.
On power up, the POR circuit requires AVDD to be present to operate. PORB is asserted low until
AVDD and DVDD and CAP are established. When AVDD, DVDD, and CAP have been established,
PORB is released high, all registers are in their default state and writes to the digital interface may
take place.
On power down, PORB is asserted low whenever DVDD or CAP drop below the minimum threshold
V
por_off
.
In most applications the time required for the device to release PORB high will be determined by the
charge time of the CAP node.
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WM8738CGED/R

Mfr. #:
Buy WM8738CGED/R
Manufacturer:
Cirrus Logic
Description:
Audio A/D Converter ICs Stereo ADC Low Power
Lifecycle:
New from this manufacturer.
Delivery:
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