LT8705
27
8705ff
For more information www.linear.com/LT8705
applicaTions inForMaTion
t
RF2
is the average of the SW2 pin rise and fall times and,
similar to t
RF1
, is typically 20ns to 40ns.
As with the M1 switch, the switching power (P
SWITCHING
)
often dominates. Look for MOSFETs with lower C
RSS
or
consider operating at a lower frequency to minimize power
loss and increase efficiency.
Switch M4: In most cases the switching power dissipa
-
tion in the M4 switch is quite small and I
2
R power losses
dominate. I
2
R power is greatest in the boost region where
the switch operates as the synchronous rectifier. Lower
V
IN
and higher V
OUT
increases the inductor current for a
given I
OUT
, leading to the highest power consumption.
The M4 switch power consumption in the boost region
can be approximated as:
P
(M4,BOOST)
≅
V
OUT
V
IN
•I
OUT
2
•ρ
τ
•R
DS(ON)
W
Gate Resistors: In some cases it can be beneficial to add
1Ω to 10Ω of resistance between some of the NMOS gate
pins and their respective gate driver pins on the LT8705
(i.e., TG1, BG1, TG2, BG2). Due to parasitic inductance
and capacitance, ringing can occur on SW1 or SW2 when
low capacitance MOSFETs are turned on/off too quickly.
The ringing can be of greatest concern when operating
the MOSFETs or the LT8705 near the rated voltage limits.
Additional gate resistance slows the switching speed,
minimizing the ringing.
Excessive gate resistance can have two negative side ef-
fects on performance:
1.
Slowing the switch transition times can also increase
power dissipation in the switch. This is described above
in the Switch M1 and Switch M3 sections.
2. Capacitive coupling from the SW1 or SW2 pin to the
switch gate node can turn it on when it’s supposed to be
off, thus increasing power dissipation. With too much
gate resistance, this would most commonly happen to
the M2 switch when SW1 is rising.
Careful board evaluation should be performed when
optimizing the gate resistance values. SW1 and SW2 pin
ringing can be affected by the inductor current levels,
therefore board evaluation should include measurements
at a wide range of load currents. When performing PCB
measurements of the SW1 and SW2 pins, be sure to use a
very short ground post from the PCB ground to the scope
probe ground sleeve in order to minimize false inductive
voltages readings.
C
IN
and C
OUT
Selection
Input and output capacitance is necessary to suppress
voltage ripple caused by discontinuous current moving in
and out of the regulator. A parallel combination of capaci
-
tors is typically used to achieve high capacitance and low
ESR
(equivalent series resistance). Dry tantalum, special
polymer, aluminum electrolytic and ceramic capacitors are
all available in surface mount packages. Capacitors with
low ESR and high ripple current ratings, such as OS-CON
and POSCAP are also available.
Ceramic capacitors should be placed near the regulator
input and output to suppress high frequency switching
spikes. A ceramic capacitor, of at least 1µF, should also
be placed from V
IN
to GND as close to the LT8705 pins
as possible. Due to their excellent low ESR characteristics
ceramic capacitors can significantly reduce input ripple
voltage and help reduce power
loss in the higher ESR bulk
capacitors. X5R or X7R dielectrics are preferred, as these
materials retain their capacitance over wide voltage and
temperature ranges. Many ceramic capacitors, particularly
0805 or 0603 case sizes, have greatly reduced capacitance
at the desired operating voltage.
Input Capacitance: Discontinuous input current is highest
in the buck region due to the M1 switch toggling on and off.
Make sure that the C
IN
capacitor network has low enough
ESR and is sized to handle the maximum RMS current.
For buck operation, the input RMS current is given by:
I
RMS
≅I
OUT(MAX)
•
V
OUT
V
IN
•
V
IN
V
OUT
–1
This formula has a maximum at V
IN
= 2V
OUT
, where
I
RMS
= I
OUT(MAX)
/2. This simple worst-case condition
is commonly used for design because even significant
deviations do not offer much relief.
