VEML6040
www.vishay.com
Vishay Semiconductors
Rev. 1.6, 21-Nov-16
6
Document Number: 84276
For technical questions, contact: sensorstechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
TYPICAL PERFORMANCE CHARACTERISTICS (T
amb
= 25 °C, unless otherwise specified)
Fig. 5 - Normalized Spectral Response
Fig. 6 - Normalized Output vs. View Angle
APPLICATION INFORMATION
Pin Connection with the Host
VEML6040 integrates R, G, B, and W sensor together with I
2
C interface. It is very easy for the baseband (CPU) to access
VEML6040 output data via I
2
C interface without extra software algorithms. The hardware schematic is shown in the following
diagram.
The 0.1 μF capacitor near the V
DD
pin is used for power supply noise rejection. The 2.2 kΩs are suitable for the pull-up resistors
of I
2
C.
Fig. 7 - Hardware Pin Connection Diagram
10
100
1000
10000
0
0.1
0.4
1.0
400 1000
Average Gain 1
Transient Thermal Impedance
Transient Thermal Impedance
Relative Responsivity (µW/cm
2
)
Normalized Response
2nd line
Wavelength (nm)
950900850800750700650600550500450
0.9
0.8
0.7
0.6
Blue
Red
Green
0.5
0.3
0.2
White
SDA (2)
SCL (3)
GND (1)
V
DD
(4)
C1
100 nF
2.5 V to 3.6 V
1.7 V to 3.6 V
R2R1
VEML6040
I
2
C bus data SDA
I
2
C bus clock SCL
Host
Micro Controller
