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NBSG16BA

P1-P3P4-P6P7-P9P10-P12
© Semiconductor Components Industries, LLC, 2014
June, 2014 − Rev. 20
1 Publication Order Number:
NBSG16/D
NBSG16
2.5 V/3.3 V SiGe Differential
Receiver/Driver with
RSECL* Outputs
*Reduced Swing ECL
Description
The NBSG16 is a differential receiver/driver targeted for high
frequency applications. The device is functionally equivalent to the
EP16 and LVEP16 devices with much higher bandwidth and lower
EMI capabilities.
Inputs incorporate internal 50 W termination resistors and accept
NECL (Negative ECL), PECL (Positive ECL), HSTL, LVTTL,
LVCMOS, CML, or LVDS. Outputs are RSECL (Reduced Swing
ECL), 400 mV.
The V
BB
and V
MM
pins are internally generated voltage supplies
available to this device only. The V
BB
is used as a reference voltage
for single-ended NECL or PECL inputs and the V
MM
pin is used as
a reference voltage for LVCMOS inputs. For all single-ended input
conditions, the unused complementary differential input is connected
to V
BB
or V
MM
as a switching reference voltage. V
BB
or V
MM
may
also rebias AC coupled inputs. When used, decouple V
BB
and V
MM
via a 0.01 mF capacitor and limit current sourcing or sinking to
0.5 mA. When not used, V
BB
and V
MM
outputs should be left open.
Features
• Maximum Input Clock Frequency > 12 GHz Typical
• Maximum Input Data Rate > 12 Gb/s Typical
• 120 ps Typical Propagation Delay
• 40 ps Typical Rise and Fall Times
• RSPECL Output with Operating Range: V
CC
= 2.375 V to 3.465 V
with V
EE
=0 V
• RSNECL Output with RSNECL or NECL Inputs with
Operating Range: V
CC
= 0 V with V
EE
= −2.375 V to −3.465 V
• RSECL Output Level (400 mV Peak-to-Peak Output), Differential
Output Only
• 50 W Internal Input Termination Resistors
• Compatible with Existing 2.5 V/3.3 V LVEP, EP, and LVEL Devices
• V
BB
and V
MM
Reference Voltage Output
• These are Pb-Free Devices
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb-Free Package
MARKING DIAGRAMS*
QFN−16
MN SUFFIX
CASE 485G
http://onsemi.com
*For additional marking information, refer to
Application Note AND8002/D.
See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.
ORDERING INFORMATION
(Note: Microdot may be in either location)
16
SG
16
ALYWG
G
1
NBSG16
http://onsemi.com
2
V
EE
NC NC V
EE
V
EE
V
BB
V
MM
V
EE
V
CC
Q
Q
V
CC
VTD
D
D
VTD
5678
16 15 14 13
12
11
10
9
1
2
3
4
NBSG16
Exposed Pad (EP)
Figure 1. QFN−16 Pinout (Top View)
Table 1. PIN DESCRIPTION
Pin Name I/O Description
1 VTD −
Internal 50 W Termination Pin. See Table 2.
2 D ECL, CML,
LVCMOS, LVDS,
LVTTL Input
Inverted Differential Input. Internal 75 kW to V
EE
and 36.5 kW to V
CC
.
3 D ECL, CML,
LVCMOS, LVDS,
LVTTL Input
Noninverted differential input. Internal 75 kW to V
EE
4 VTD −
Internal 50 W Termination Pin. See Table 2.
5, 8,
13, 16
V
EE
− Negative Supply Voltage
6,7 NC − No Connect
9, 12 V
CC
− Positive Supply Voltage
10 Q RSECL Output
Noninverted Differential Output. Typically Terminated with 50 W to V
TT
= V
CC
− 2 V
11 Q RSECL Output
Inverted Differential Output. Typically Terminated with 50 W to V
TT
= V
CC
− 2 V
14 V
MM
− LVCMOS Reference Voltage Output. (V
CC
− V
EE
)/2
15 V
BB
− ECL Reference Voltage Output
− EP − The Exposed Pad (EP) on the QFN−16 package bottom is thermally connected to the die for
improved heat transfer out of package. The exposed pad must be attached to a heat-sinking
conduit. The pad is not electrically connected to the die but may be electrically and thermally
connected to V
EE
on the PC board.
1. All V
CC
and V
EE
pins must be externally connected to Power Supply to guarantee proper operation. The thermally exposed pad on package
bottom (see case drawing) must be attached to a heat-sinking conduit.
2. In the differential configuration when the input termination pins (VTD, VTD
) are connected to a common termination voltage, and if no signal
is applied then the device will be susceptible to self-oscillation.
NBSG16
http://onsemi.com
3
50 W
50 W
VTD
D
D
VTD
V
MM
Q
Q
V
BB
V
EE
V
CC
Figure 2. Logic Diagram
75 kW 75 kW
36.5 KW
Table 2. INTERFACING OPTIONS
INTERFACING OPTIONS CONNECTIONS
CML Connect VTD and VTD to V
CC
LVDS Connect VTD and VTD together
AC−COUPLED Bias VTD and VTD Inputs within (V
IHCMR
)
Common Mode Range
RSECL, PECL, NECL Standard ECL Termination Techniques
LVTTL The external voltage should be applied to the
unused complementary differential input.
Nominal voltage is 1.5 V for LVTTL.
LVCMOS V
MM
should be connected to the unused
complementary differential input.
Table 3. ATTRIBUTES
Characteristics Value
Internal Input Pulldown Resistor (D, D)
75 kW
Internal Input Pullup Resistor (D)
36.5 kW
ESD Protection Human Body Model
Machine Model
> 2 kV
> 100 V
Moisture Sensitivity (Note 3) Pb-Free Level 1
Flammability Rating Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in
Transistor Count 167
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
3. For additional information, see Application Note AND8003/D.
P1-P3P4-P6P7-P9P10-P12

NBSG16BA

Mfr. #:
Buy NBSG16BA
Manufacturer:
ON Semiconductor
Description:
Buffers & Line Drivers 2.5V/3.3V SiGe Diff
Lifecycle:
New from this manufacturer.
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