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Table 7. DC CHARACTERISTICS, NECL or RSNECL INPUT WITH NECL OUTPUT
(V
CC
= 0 V; V
EE
= −3.465 V to −2.375 V) (Note 17)
Symbo
l
Characteristic
−40°C 25°C 85°C
Unit
Min Typ Max Min Typ Max Min Typ Max
POWER SUPPLY CURRENT
I
EE
Negative Power Supply Current 17 23 29 17 23 29 17 23 29 mA
RSPECL OUTPUTS (Note 18)
V
OH
Output HIGH Voltage −1050 −970 −925 −975 −935 −900 −950 −910 −875 mV
V
OUTPP
Output Voltage Amplitude 350 410 525 350 410 525 350 410 525 mV
DIFFERENTIAL CLOCK INPUTS DRIVEN SINGLE-ENDED (Figures 5 & 7) (Note 19)
V
IH
Input HIGH Voltage V
EE
+
1200
V
CC
V
EE
+
1200
V
CC
V
EE
+
1200
V
CC
mV
V
IL
Input LOW Voltage V
EE
V
IH
150
V
EE
V
IH
150
V
EE
V
IH
150
mV
V
th
Input Threshold Voltage Range
(Note 20)
V
EE
+
950
V
CC
75
V
EE
+
950
V
CC
75
V
EE
+
950
V
CC
75
mV
V
ISE
Single-Ended Input Voltage
(V
IH
– V
IL
)
150 2600 150 2600 150 260 mV
V
BB
NECL Output Voltage Reference −1420 −1360 −1300 −1420 −1360 −1300 −1420 −1360 −1300 mV
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Figures 6 & 8) (Note 21)
V
IHD
Differential Input HIGH Voltage V
EE
+
1200
V
CC
V
EE
+
1200
V
CC
V
EE
+
1200
V
CC
mV
V
ILD
Differential Input LOW Voltage V
EE
V
IHD
75
V
EE
V
IHD
75
V
EE
V
IHD
75
mV
V
ID
Differential Input Voltage
(V
IHD
– V
ILD
)
75 2600 75 2600 75 2600 mV
V
IHCMR
Input HIGH Voltage Common Mode
Range (Note 22) (Figure 9)
V
EE
+
1200
0 V
EE
+
1200
0 V
EE
+
1200
0 mV
I
IH
Input HIGH Current (@V
IH
) 30 100 30 100 30 100
mA
I
IL
Input LOW Current (@V
IL
) 25 50 25 50 25 50
mA
LVCMOS CONTROL PIN (Note 23)
V
MM
CMOS Output Voltage Reference
V
CC
/2
V
MM
150
V
MM
V
MM
+
150
V
MM
150
V
MM
V
MM
+
150
V
MM
150
V
MM
V
MM
+
150
mV
TERMINATION RESISTORS
R
TIN
Internal Input Termination Resistor 45 50 55 45 50 55 45 50 55
W
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
17.Input and output parameters vary 1:1 with V
CC
.
18.All loading with 50 W to V
CC
− 2.0 V.
19.V
th
, V
IH
, V
IL,
and V
ISE
parameters must be complied with simultaneously.
20.V
th
is applied to the complementary input when operating in single-ended mode. V
th
= (V
IH
− V
IL
) / 2.
21.V
IHD
, V
ILD,
V
ID
and V
IHCMR
parameters must be complied with simultaneously.
22.V
IHCMR
min varies 1:1 with V
EE
, V
IHCMR
max varies 1:1 with V
CC
. The V
IHCMR
range is referenced to the most positive side of the differential
input signal.
23.V
MM
typical = |V
CC
− V
EE
|/2 + V
EE
= V
MMT
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Table 8. AC CHARACTERISTICS
(V
CC
= 0 V; V
EE
= −3.465 V to −2.375 V or V
CC
= 2.375 V to 3.465 V; V
EE
= 0 V)
Symbo
l
Characteristic
−40°C 25°C 85°C
Uni
t
Min Typ Max Min Typ Max Min Typ Max
f
max
Maximum Input Clock Frequency
(See Figure 3. f
max
/JITTER) (Note 24)
10.7 12 10.7 12 10.7 12 GHz
t
PLH
,
t
PHL
Propagation Delay to
Output Differential
90 110 130 100 120 140 95 125 145 ps
t
SKEW
Duty Cycle Skew (Note 25) 3 15 3 15 3 15 ps
t
JITTER
RMS Random Clock Jitter
f
in
< 10 GHz
Peak−to−Peak Data Dependent Jitter
f
in
< 10 Gb/s
0.2
8
2 0.2
8
2 0.2
8
2
ps
V
INPP
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 26)
75 2600 75 2600 75 2600 mV
t
r
t
f
Output Rise/Fall Times @ 1 GHz Q, Q
(20% − 80%)
20 30 50 20 30 50 20 30 50 ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
24.Measured using a 400 mV source, 50% duty cycle clock source. All loading with 50 W to V
CC
− 2.0 V. Input edge rates 40 ps (20% − 80%).
25.See Figure 10. t
skew
= |t
PLH
− t
PHL
| for a nominal 50% differential clock input waveform.
26.V
INPP(max)
cannot exceed V
CC
− V
EE
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OUTPUT AMP
RMS JITTER
INPUT FREQUENCY (GHz)
Figure 3. Output Voltage Amplitude (V
OUTPP
) / RMS Jitter vs.
Input Frequency (f
in
) at Ambient Temperature (Typical)
OUTPUT VOLTAGE AMPLITUDE (mV)
JITTER
OUT
ps (RMS)
700
600
500
400
300
200
100
0
1413121110987654321
9.5
8.5
7.5
6.5
3.5
2.5
5.5
4.5
0.5
−0.5
1.5
Q
Q
Figure 4. 10.709 Gb/s Diagram (3.0 V, 255 C)
X = 17ps/Div Y = 70 mV/Div

NBSG16BA

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Buffers & Line Drivers 2.5V/3.3V SiGe Diff
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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