LTC3619
13
3619fa
applicaTions inForMaTion
derate the capacitor, or choose a capacitor rated at a higher
temperature than required. Several capacitors may also be
paralleled to meet the size or height requirements of the
design. An additional 0.1µF toF ceramic capacitor is
also recommended on V
IN
for high frequency decoupling
when not using an all-ceramic capacitor solution.
Output Capacitor (C
OUT
) Selection
The selection of C
OUT
is driven by the required effective
series resistance (ESR). Typically, once the ESR require-
ment for C
OUT
has been met, the RMS current rating
generally far exceeds the I
RIPPLE(P-P)
requirement. The
output ripple DV
OUT
is determined by:
V
OUT
I
L
ESR +
1
8f
O
C
OUT
where f
O
= operating frequency, C
OUT
= output capacitance
and DI
L
= ripple current in the inductor. For a fixed output
voltage, the output ripple is highest at maximum input
voltage since DI
L
increases with input voltage.
If tantalum capacitors are used, it is critical that the capaci-
tors are surge tested for use in switching power supplies.
An excellent choice is the AVX TPS series of surface mount
tantalum. These are specially constructed and tested for
low ESR so they give the lowest ESR for a given volume.
Other capacitor types include Sanyo POSCAP, Kemet
KO-CAP, and Sprague 593D and 595D series. Consult the
manufacturer for other specific recommendations.
Using Ceramic Input and Output Capacitors
Higher values, lower cost ceramic capacitors are now
becoming available in smaller case sizes. Their high ripple
current, high voltage rating and low ESR make them ideal
for switching regulator applications. Because the LTC3619
control loop does not depend on the output capacitor’s ESR
for stable operation, ceramic capacitors can be used freely
to achieve very low output ripple and small circuit size.
However, care must be taken when ceramic capacitors are
used at the input. When a ceramic
capacitor is used at the
input
and the power is supplied by a wall adapter through
Table 1. Representative Surface Mount Inductors
MANUFACTURER PART NUMBER VALUE MAX DC CURRENT DCR HEIGHT
Coilcraft LPS4012-152ML
LPS4012-222ML
LPS4012-332ML
LPS4012-472ML
LPS4018-222ML
LPS4018-332ML
LPS4018-472ML
1.5µH
2.2µH
3.3µH
4.7µH
2.2µH
3.3µH
4.7µH
2200mA
1750mA
1450mA
1450mA
2300mA
2000mA
1800mA
0.070Ω
0.100Ω
0.100Ω
0.170Ω
0.070Ω
0.080Ω
0.125Ω
1.2mm
1.2mm
1.2mm
1.2mm
1.8mm
1.8mm
1.8mm
FDK FDKMIPF2520D
FDKMIPF2520D
FDKMIPF2520D
4.7µH
3.3µH
2.2µH
1100mA
1200mA
1300mA
0.11Ω
0.1Ω
0.08Ω
1mm
1mm
1mm
Murata
LQH32CN4R7M23
4.7µH 450mA 0.2Ω 2mm
Panasonic ELT5KT4R7M 4.7µH 950mA 0.2Ω 1.2mm
Sumida CDRH2D18/LD
CDH38D11SNP-3R3M
CDH38D11SNP-2R2M
4.7µH
3.3µH
2.2µH
630mA
1560mA
1900mA
0.086Ω
0.115Ω
0.082Ω
2mm
1.2mm
1.2mm
Taiyo Yuden CB2016T2R2M
CB2012T2R2M
CB2016T3R3M
NR30102R2M
NR30104R7M
2.2µH
2.2µH
3.3µH
2.2µH
4.7µH
510mA
530mA
410mA
1100mA
750mA
0.13Ω
0.33Ω
0.27Ω
0.1Ω
0.19Ω
1.6mm
1.25mm
1.6mm
1mm
1mm
TDK VLF3010AT4R7-MR70
VLF3010AT3R3-MR87
VLF3010AT2R2-M1R0
VLF4012AT-2R2M1R5
VLF5012ST-3R3M1R7
VLF5014ST-2R2M2R3
4.7µH
3.3µH
2.2µH
2.2µH
3.3µH
2.2µH
700mA
870mA
1000mA
1500mA
1700mA
2300mA
0.28Ω
0.17Ω
0.12Ω
0.076Ω
0.095Ω
0.059Ω
1mm
1mm
1mm
1.2mm
1.2mm
1.4mm
LTC3619
14
3619fa
applicaTions inForMaTion
long wires, a load step at the output can induce ringing at
the input, V
IN
. At best, this ringing can couple to the output
and be mistaken as loop instability. At worst, a sudden
inrush of current through the long wires can potentially
cause a voltage spike at V
IN
, large enough to damage the
part. For more information, see Application Note 88.
When choosing the input and output ceramic capacitors,
choose the X5R or X7R dielectric formulations. These
dielectrics have the best temperature and voltage char-
acteristics of all the ceramics for a given value and size.
Setting the Output Voltage
The LTC3619 regulates the V
FB1
and V
FB2
pins to 0.6V
during regulation. Thus, the output voltage is set by a resis-
tive divider, Figure 2, according to the following formula:
V
OUT
= 0.6V 1+
R2
R1
(2)
Keeping the current small (<10µA) in these resistors
maximizes efficiency, but making it too small may allow
stray capacitance to cause noise problems or reduce the
phase margin of the error amp loop.
To improve the frequency response of the main control
loop, a feedback capacitor (C
F
) may also be used. Great
care should be taken to route the V
FB
line away from noise
sources, such as the inductor or the SW line.
Checking Transient Response
The regulator loop response can be checked by looking
at the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, V
OUT
immediately shifts by an amount
equal to DI
LOAD
ESR, where ESR is the effective series
resistance of C
OUT
. DI
LOAD
also begins to charge or dis-
charge C
OUT
generating a feedback error signal used by the
regulator to return V
OUT
to its steady-state value. During
this recovery time, V
OUT
can be monitored for overshoot
or ringing that would indicate a stability problem.
The initial output voltage step may not be within the
bandwidth of the feedback loop, so the standard second
order overshoot/DC ratio cannot be used to determine the
phase margin. In addition, feedback capacitors (C
F1
and
C
F2
) can be added to improve the high frequency response,
as shown in Figure 2. Capacitor C
F
provides phase lead by
creating a high frequency zero with R2 which improves
the phase margin.
The output voltage settling behavior is related to the stability
of the closed-loop system and will demonstrate the actual
overall supply performance. For a detailed explanation of
optimizing the compensation components, including a
review of control loop theory, refer to Application Note 76.
In some applications, a more severe transient can be caused
by switching in loads with large (>1µF) input capacitors.
The discharged input capacitors are effectively put in paral-
lel with C
OUT
, causing a rapid drop in V
OUT
. No regulator
can deliver enough current to prevent this problem if the
switch connecting the load has low resistance and is driven
quickly. The solution is to limit the turn-on speed of the
load switch driver. A Hot Swap™ controller is designed
specifically for this purpose and usually incorporates cur-
rent limiting, short-circuit protection, and soft-starting.
Efficiency Considerations
The percent efficiency of a switching
regulator is equal to
the
output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can
be expressed as:
% Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc., are the individual losses as a percent-
age of input power.
Although all dissipative elements in the circuit produce
losses, four sources usually account for the losses in
LTC3619 circuits: 1) V
IN
quiescent current, 2) switching
losses, 3) I
2
R losses, 4) other system losses.
1. The V
IN
current is the DC supply current given in the
Electrical Characteristics which excludes MOSFET
driver and control currents. V
IN
current results in a
small (<0.1%) loss that increases with V
IN
, even at
no load.
2. The switching current is the sum of the MOSFET driver
and control currents. The MOSFET driver current re-
LTC3619
15
3619fa
applicaTions inForMaTion
sults from switching the gate capacitance of the power
MOSFETs. Each time a MOSFET gate is switched from
low to high to low again, a packet of charge dQ moves
from V
IN
to ground. The resulting dQ/dt is a current
out of V
IN
that is typically much larger than the DC bias
current. In continuous mode, I
GATECHG
= f
O
(Q
T
+ Q
B
),
where Q
T
and Q
B
are the gate charges of the internal
top and bottom MOSFET switches. The gate charge
losses are proportional to V
IN
and thus their effects
will be more pronounced at higher supply voltages.
3. I
2
R losses are calculated from the DC resistances of
the internal switches, R
SW
, and external inductor, R
L
.
In continuous mode, the average output current flows
through inductor L, but ischopped” between the internal
top and bottom switches. Thus, the series resistance
looking into the SW pin is a function of both top and
bottom MOSFET R
DS(ON)
and the duty cycle (DC) as
follows:
R
SW
= (R
DS(ON)TOP
) • (DC) + (R
DS(ON)BOT
) • (1– DC)
The R
DS(ON)
for both the top and bottom MOSFETs can be
obtained from the Typical Performance Characteristics
cur
ves. Thus, to obtain I
2
R losses:
I
2
R losses = I
OUT
2
• (R
SW
+ R
L
)
4. Otherhidden” losses, such as copper trace and internal
battery resistances, can account for additional efficiency
degradations in portable systems. It is very important
to include thesesystem” level losses in the design of a
system. The internal battery and fuse resistance losses
can be minimized by making sure that C
IN
has adequate
charge storage and very low ESR at the switching fre-
quency. Other losses, including diode conduction losses
during dead-time, and inductor core losses, generally
account for less than 2% total additional loss.
Thermal Considerations
In a majority of applications, the LTC3619 does not dis-
sipate much heat due to its high efficiency. In the unlikely
event that the junction temperature somehow reaches ap-
proximately 150°C, both power switches will be turned off
and the SW node will become high impedance. The goal
of the following thermal analysis is to determine whether
the power dissipated causes enough temperature rise to
exceed the maximum junction temperature (125°C) of the
part. The temperature rise is given by:
T
RISE
= P
D
θ
JA
where P
D
is the power dissipated by the regulator and
θ
JA
is the thermal resistance from the junction of the die
to the ambient temperature. The junction temperature,
T
J
, is given by:
T
J
= T
RISE
+ T
AMBIENT
As a worst-case example, consider the case when the
LTC3619 is in dropout on both channels at an input volt-
age of 2.7V with a load current of 400mA and 800mA
and an ambient temperature of 70°C. From the Typical
Performance Characteristics graph of Switch Resistance,
the R
DS(ON)
of the switch is 0.58Ω and 0.33Ω. Therefore,
power dissipated by each channel is:
P
D1
= I
OUT
2
R
DS(ON)
= 93mV
P
D2
= I
OUT
2
R
DS(ON)
= 212mV
Given that the thermal resistance of a properly soldered
DFN package is approximately 40°C/W, the junction
temperature of an LTC3619 device operating in a 70°C
ambient temperature is approximately:
T
J
= (0.305W • 40°C/W) + 70°C = 82.2°C
which is well below the absolute maximum junction tem-
perature of 125°C.
PC Board Layout Considerations
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3619. These items are also illustrated graphically
in the layout diagrams of Figures 3a and 3b. Check
the
following in your layout:
1.
Does the capacitor C
IN
connect to the power V
IN
(Pin 6)
and GND (Pin 11) as closely as possible? This capacitor
provides the AC current of the internal power MOSFETs
and their drivers.
2. Are the respective C
OUT
and L closely connected? The
(–) plate of C
OUT
returns current to GND and the (–)
plate of C
IN
.

LTC3619IDD#PBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators 400mA/800mA Synchronous Step-Down DC/DC Converter with Average Input Current Limit
Lifecycle:
New from this manufacturer.
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