LTC3619
9
3619fa
operaTion
The LTC3619 uses a constant-frequency, current mode
architecture. The operating frequency is set at 2.25MHz.
Both channels share the same clock and run in-phase.
The output voltage is set by an external resistor divider
returned to the V
FB
pins. An error amplifier compares the
divided output voltage with a reference voltage of 0.6V and
regulates the peak inductor current accordingly.
The LTC3619 continuously monitors the input current
of both channels. When the sum of the currents of both
channels exceeds the programmed input current limit set
by an external resistor, R
LIM
, channel 2 is current limited
while channel 1 remains regulated.
Main Control Loop
During normal operation, the top power switch (P-channel
MOSFET) is turned on at the beginning of a clock cycle
when the V
FB
voltage is below the reference voltage. The
current into the inductor and the load increases until the
peak inductor current (controlled by I
TH
) is reached. The
RS latch turns off the synchronous switch and energy
stored in the inductor is discharged through the bottom
switch (N-channel MOSFET) into the load until the next
clock cycle begins, or until the inductor current begins to
reverse (sensed by the I
RCMP
comparator).
The peak inductor current is controlled by the internally
compensated I
TH
voltage, which is the output of the er-
ror amplifier. This amplifier regulates the V
FB
pin to the
internal 0.6V reference by adjusting the peak inductor
current accordingly.
When the input current limit is engaged, the peak inductor
current will be lowered, which then reduces the switch-
ing duty cycle and V
OUT
. This allows the input voltage
to stay regulated when its programmed current output
capability is met.
Light Load Operation
The LTC3619 will automatically transition from continuous
operation to Burst Mode operation when the load current is
low. During relatively light loads, the peak inductor current
(as set by I
TH
) remains fixed at approximately 60mA and
120mA for channel 1 and channel 2, respectively. The PMOS
switch operates intermittently based on load demand. By
running cycles periodically, the switching losses are mini-
mized. The duration of each burst event can range from a
few cycles at light load to almost continuous cycling with
short sleep intervals at moderate loads. During the sleep
intervals, the load current is being supplied solely from
the output capacitor. A majority of the internal circuitry
is shut off to conserve quiescent
current. As the output
voltage droops, the error amplifier output rises above the
sleep threshold, signaling the burst comparator to un-trip
and turns the top MOSFET on. This cycle repeats at a rate
that is dependent on load demand.
Dropout Operation
When the input supply voltage decreases toward the
output voltage the duty cycle increases to 100%, which
is the dropout condition. In dropout, the PMOS switch is
turned on continuously with the output voltage being equal
to the input voltage minus the voltage drops across the
internal P-channel MOSFET and the inductor.
An important design consideration is that the R
DS(ON)
of the P-channel switch increases with decreasing input
supply voltage (see Typical Performance Characteristics).
Therefore, the user should calculate the worst-case power
dissipation when the LTC3619 is used at 100% duty cycle
with low input voltage (see Thermal Considerations in the
Applications Information section).
Soft-Start
In order to minimize the inrush current on the input bypass
capacitor, the LTC3619 slowly ramps up the output volt-
age during start-up. Whenever the RUN1 or RUN2 pin is
pulled high, the corresponding output will ramp from zero
to full-scale over a time period of approximately 950µ
s.
This prevents the LTC3619 from having to quickly charge
the output capacitor and thus supplying an excessive
amount of instantaneous current.
