MAX520/MAX521
Quad/Octal, 2-Wire Serial 8-Bit DACs
with Rail-to-Rail Outputs
______________________________________________________________________________________ 13
Setting the RST bit high clears all DAC input latches.
The DAC outputs remain unchanged until a STOP con-
dition is detected (Figure 10a). If a reset is issued, the
following output byte is ignored. Subsequent pairs of
command/output bytes overwrite the input latches
(Figure 10b).
All changes made during a transmission affect the
MAX520/MAX521’s outputs only when the transmission
ends and a STOP has been recognized. The R0, R1,
and R2 bits are reserved bits that must be set to zero.
I
2
C Compatibility
The MAX520/MAX521 are fully compatible with existing
I
2
C systems. SCL and SDA are high-impedance inputs;
SDA has an open drain which pulls the data line low
during the 9th clock pulse. Figure 11 shows a typical
I
2
C application.
Additional START Conditions
It is possible to interrupt a transmission to a MAX520/
MAX521 with a new START (repeated start) condition
(perhaps addressing another device), which leaves the
input latches with data that has not been transferred to
the output latches (Figure 12). Only the currently
addressed device will recognize a STOP condition and
transfer data to its output latches. If the device is left
with data in its input latches, the data can be trans-
ferred to the output latches the next time the device is
addressed, as long as it receives at least one com-
mand byte and a STOP condition.
( )
( )
( )
SDA
0
START
CONDITION
ADDRESS BYTE ACK
101 AD1AD00000010 0
(RST)
(RST)
STOP
CONDITION
COMMAND BYTE
ACK
ALL OUTPUTS 
SET TO 0
( )
ALL INPUT LATCHES
SET TO 0
ALL INPUT LATCHES
SET TO 0
SDA
0
START
CONDITION
ADDRESS BYTE ACK
101 AD1AD00000010 0 0
STOP
CONDITION
COMMAND BYTE
ACK
"DUMMY"
OUTPUT BYTE
ACK
(a)
(b)
ALL DAC OUTPUTS SET TO 0 UNLESS 
CHANGED BY ADDITIONAL COMMAND 
BYTE/OUTPUT BYTE PAIRS
NOTE: X = DON'T CARE
ADDITIONAL 
COMMAND BYTE/
OUTPUT BYTE PAIRS
X X X
X X X X X X X X X X X
0 OR AD2
0 OR AD2
Figure 10. Resetting DAC Outputs
MAX520
SDA SCL
µC
SDA
SCL
E
2
PROM
XICOR
X24C04
SDA
SCL
AD1
AD2
AD0
QUAD
DAC
SDA
SCL
AD1
AD0
OCTAL
DAC
+5V
MAX521
Figure 11. Typical I
2
C Application Circuit
MAX520/MAX521
Quad/Octal, 2-Wire Serial 8-Bit DACs
with Rail-to-Rail Outputs
14 ______________________________________________________________________________________
Early Stop Conditions
The addressed device recognizes a STOP condition at
any point in a transmission. If the STOP occurs during a
command byte, all previous uninterrupted command
and output byte pairs are accepted, the interrupted
command byte is ignored, and the transmission ends
(Figure 13a). If the STOP occurs during an output byte,
all previous uninterrupted command and output byte
pairs are accepted, the final command byte
s PD and
RST bits are accepted, the interrupted output byte is
ignored, and the transmission ends (Figure 13b).
Analog Section
DAC Operation
The MAX520 contains four matched voltage-output
DACs, and the MAX521 contains eight. The DACs are
inverted R-2R ladder networks that convert 8-bit digital
words into equivalent analog output voltages in propor-
tion to the applied reference voltages. For both
devices, DAC0–DAC3 each have separate reference
inputs, while the MAX521’s DAC4–DAC7 all share a
common reference input. Figure 14 shows a simplified
diagram of one DAC.
Reference Inputs
The MAX520/MAX521 can be used for multiplying appli-
cations. The reference accepts a 0V to V
DD
voltage,
both DC and AC signals. The voltage at each REF input
sets the full-scale output voltage for its respective
DAC(s). The reference voltage must be positive. The
DAC’s input impedance is code dependent, with the
lowest value occurring when the input code is 55 hex or
0101 0101, and the maximum value occurring when the
input code is 00 hex. Since the REF input resistance
( )
( )
( )
SDA
0
START
CONDITION
ADDRESS BYTE
(DEVICE 0)
ACK
10100000 0
0
00000001 0101001001
REPEATED START
CONDITION
STOP
CONDITION
COMMAND BYTE
ADDRESSING DAC1
COMMAND BYTE
(ADDRESSING DAC2)
ACK
OUTPUT BYTE
(FULL SCALE)
ACK
ADDRESS BYTE
(DEVICE 1)
ACK
DEVICE 0's
DAC1 INPUT LATCH
SET TO FULL SCALE
DEVICE 1's
DAC2 INPUT LATCH
SET TO FULL SCALE
SDA
ACK ACK
OUTPUT BYTE
(FULL SCALE)
ONLY DEVICE 1's DAC2 OUTPUT LATCH SET TO FULL 
SCALE. DEVICE 0's OUTPUT LATCHES UNCHANGED.
1111 111
000000 00 0111111 111
Figure 12. Repeated START Conditions
( )
SDA
00
START
CONDITION
ADDRESS BYTE ACK
1 1 AD1 AD0 0 0 0 0 0011
(RST) (PD)
(PD)
EARLY
STOP CONDITION
INTERRUPTED
COMMAND BYTE
MAX520/MAX521's STATES
REMAIN UNCHANGED
( )
SDA
0
START
CONDITION
ADDRESS BYTE ACK
101 AD1AD000000 000011100RST 1
COMMAND BYTE
(POWER DOWN)
ACK
INTERRUPTED
OUTPUT BYTE
(a)
(b)
MAX520/MAX521 POWER DOWN;
INPUT LATCHES UNCHANGED IF 
RST = 0, DAC OUTPUTS RESET IF
RST = 1.
EARLY
STOP CONDITION
0 OR AD2
0 OR AD2
Figure 13. Early STOP Conditions
MAX520/MAX521
Quad/Octal, 2-Wire Serial 8-Bit DACs
with Rail-to-Rail Outputs
______________________________________________________________________________________ 15
(R
IN
) is code dependent, it must be driven by a circuit
with low output impedance (no more than R
IN
÷ 2000) to
maintain output linearity. The REF input capacitance is
also code dependent, with the maximum value occur-
ring at code FF hex (typically 30pF for the MAX520/
MAX521’s REF0–REF3, and 120pF for the MAX521’s
REF4). The output voltage for any DAC can be repre-
sented by a digitally programmable voltage source as:
V
OUT
= (N x V
REF
) / 256, where N is the numerical value
of the DAC’s binary input code. Table 1 shows the
unipolar code.
MAX520 Unbuffered DAC Outputs
The unbuffered DAC outputs (OUT0–OUT3) connect
directly to the internal 16kR-2R network. The outputs
swing from 0V to V
DD
.
The MAX520 has no output buffer amplifiers, giving it
very low supply current. The output-offset voltage is
lower without the output buffer, and the output can also
slew and settle faster if capacitive loading is minimized.
Resistive loading should be very light for highest accu-
racy. Any output loading generates some gain error,
increasing full-scale error. The R-2R ladder’s output
resistance is 16k, so a 1µA output current creates a
16mV error. Linearity is not affected because the ladder
output resistance does not change with DAC code.
Ladder-resistance changes with temperature are also
very small.
DACs are often used in trimming applications to
replace hardware potentiometers. Figure 15a shows a
typical application, which requires a buffered output so
that a precise current can be injected into the summing
node through precision resistor R
T
. For this application,
the MAX520A features a precise ±1% (T
A
= +25°C,
±2.5% over temperature) factory-trimmed output resis-
tance. Because the MAX520A’s output resistance is
precisely trimmed, there is no need for an internal
buffer or external precision resistor (Figure 15b). For
applications where the output resistance value is not
critical, use the MAX520B.
All DACs exhibit output glitches during code transitions.
An output filter is sometimes used to reduce these
glitches in sensitive applications. The MAX520 simpli-
fies output filtering because its internal resistive ladder
network serves as the “R” in an RC filter. Simply con-
nect a small capacitor from the DAC output to ground.
See the
Typical Operating Characteristics
for oscillo-
scope photos of the worst-case 1LSB step change both
without and with 25pF of capacitance on the MAX520’s
output.
MAX521 Output Buffer Amplifiers
The MAX521 voltage outputs (OUT0–OUT7) are inter-
nally buffered precision unity-gain followers that slew
up to 1V/µs. The outputs can swing from 0V to V
DD
.
With a 0V to 4V (or 4V to 0V) output transition, the
amplifier outputs typically settle to 1/2LSB in 6µs when
loaded with 10k in parallel with 100pF. The buffer
amplifiers are stable with any combination of resistive
loads 2k and capacitive loads 300pF.
2R
R
RR
2R
2R 2R 2R 2R
D0 D5 D6 D7
REF_
AGND
SHOWN FOR ALL 1s ON DAC
OUT_
(MAX521)
OUT_
(MAX520)
Figure 14. DAC Simplified Circuit Diagram
Table 1. Unipolar Code Table
0V00000000
1
+ V
REF
(———)
256
00000001
127
+ V
REF
(———)
256
01111111
128 V
REF
+ V
REF
(———)= ——
256 2
10000000
129
+ V
REF
(———)
256
10000001
255
+ V
REF
(———)
256
11111111
ANALOG OUTPUTDAC CONTENTS

MAX521AEAG+T

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Digital to Analog Converters - DAC 8-Bit 8Ch Precision DAC
Lifecycle:
New from this manufacturer.
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